Patents by Inventor Huei-Ru Tsai
Huei-Ru Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446489Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.Type: GrantFiled: October 25, 2018Date of Patent: October 15, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
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Publication number: 20190067184Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.Type: ApplicationFiled: October 25, 2018Publication date: February 28, 2019Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
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Patent number: 10153231Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.Type: GrantFiled: March 22, 2017Date of Patent: December 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
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Patent number: 10079177Abstract: A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with H2 gas at a first pressure. The cobalt layer is treated with a H2 plasma at a second pressure. The second pressure is lower than the first pressure.Type: GrantFiled: September 1, 2017Date of Patent: September 18, 2018Assignee: United Microelectronics Corp.Inventors: Ko-Wei Lin, Ying-Lien Chen, Chun-Ling Lin, Huei-Ru Tsai, Hung-Miao Lin, Sheng-Yi Su, Tzu-Hao Liu
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Publication number: 20180261537Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.Type: ApplicationFiled: March 22, 2017Publication date: September 13, 2018Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
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Publication number: 20160276215Abstract: A method for manufacturing a semiconductor device is provided. The method comprises steps as follows. At least one trench is provided in a low-k dielectric layer on a substrate. The trench is filled with a copper (Cu) film. Pure cobalt (Co) is deposited on a surface of the Cu film by introducing a flow of a carrier gas carrying a Co-containing precursor and a reducing agent onto the surface of the Cu film. The flowrate of the flow is within a range from 5 to 19 sccm.Type: ApplicationFiled: March 18, 2015Publication date: September 22, 2016Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: PEI-TING LEE, GUO-WEI CHEN, CHUN-LING LIN, CHI-MAO HSU, CHING-WEI HSU, HUEI-RU TSAI, JIA-RONG LI, SHANG NAN CHOU, PO CHIH WU
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Patent number: 9412653Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.Type: GrantFiled: August 4, 2015Date of Patent: August 9, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Chun-Ling Lin, Huei-Ru Tsai, Ching-Wei Hsu, Chin-Fu Lin, Hsin-Yu Chen
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Publication number: 20150340280Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.Type: ApplicationFiled: August 4, 2015Publication date: November 26, 2015Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Chun-Ling Lin, Huei-Ru Tsai, Ching-Wei Hsu, Chin-Fu Lin, Hsin-Yu Chen
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Patent number: 9136170Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.Type: GrantFiled: May 30, 2012Date of Patent: September 15, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Chun-Ling Lin, Huei-Ru Tsai, Ching-Wei Hsu, Chin-Fu Lin, Hsin-Yu Chen
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Patent number: 9012324Abstract: A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.Type: GrantFiled: August 24, 2012Date of Patent: April 21, 2015Assignee: United Microelectronics Corp.Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Ching-Wei Hsu, Szu-Hao Lai, Huei-Ru Tsai, Tsai-Yu Wen, Ching-Li Yang, Chien-Li Kuo
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Publication number: 20150093893Abstract: In a process of forming a seed layer, particularly in a vertical trench or via, a semiconductor substrate having a dielectric structure and a hard mask structure thereon is provided. An opening is formed in the hard mask structure, and a trench or via is formed in the dielectric structure in communication with the opening, wherein an area of the opening is greater than that of an entrance of the trench or via. A seed layer is then deposited in the trench or via through the opening, and then subjected to a reflow process.Type: ApplicationFiled: October 2, 2013Publication date: April 2, 2015Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Yi-Fang Tao, Ching-Wei Hsu, Hsin-Yu Chen, Tsun-Min Cheng, Yung-Chien Kung, Chi-Mao Hsu, Guo-Wei Chen, Huei-Ru Tsai, Jia-Rong Li
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Publication number: 20140057434Abstract: A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.Type: ApplicationFiled: August 24, 2012Publication date: February 27, 2014Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Ching-Wei Hsu, Szu-Hao Lai, Huei-Ru Tsai, Tsai-Yu Wen, Ching-Li Yang, Chien-Li Kuo
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Publication number: 20130320537Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Chun-Ling Lin, Huei-Ru Tsai, Ching-Wei Hsu, Chin-Fu Lin, Hsin-Yu Chen