Patents by Inventor Huei-Tsz WANG

Huei-Tsz WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230397512
    Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 7, 2023
    Inventors: Huei-Tsz WANG, Po-Shu WANG, Wei-Ming WANG
  • Patent number: 11818970
    Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huei-Tsz Wang, Po-Shu Wang, Wei-Ming Wang
  • Publication number: 20220376175
    Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 24, 2022
    Inventors: Huei-Tsz WANG, Po-Shu Wang, Wei-Ming Wang
  • Patent number: 11430953
    Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huei-Tsz Wang, Po-Shu Wang, Wei-Ming Wang
  • Publication number: 20210135103
    Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 6, 2021
    Inventors: Huei-Tsz WANG, Po-Shu Wang, Wei-Ming Wang
  • Patent number: 10886465
    Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huei-Tsz Wang, Po-Shu Wang, Wei-Ming Wang
  • Publication number: 20190267544
    Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.
    Type: Application
    Filed: February 28, 2018
    Publication date: August 29, 2019
    Inventors: Huei-Tsz WANG, Po-Shu WANG, Wei-Ming WANG