Abstract: The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor; and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.

Abstract: The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor; and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.

Abstract: Provided herein are methods and kits for analyzing a sample such as a biological sample obtained from a subject having, suspected of having, or being at risk for a cancer to assess presence of cancer stem cells in the sample, which is indicative of poor cancer prognosis.

Abstract: An apparatus for observing a sample using a charged particle beam includes an ion beam column configured to generate and direct an ion beam, an electron beam column configured to generate and direct an electron beam, a vacuum chamber for housing the sample, and a probe positioned in the vacuum chamber. The probe is configured to provide electrical connection between the sample and a power supply.

Abstract: A testline structure of a semiconductor device includes a substrate layer, a frontside insulating layer atop the substrate layer, a backside insulating layer under the substrate layer, and a probe pad structure vertically extending through the frontside insulating layer, the substrate layer, and the backside insulating layer. The probe pad structure includes a frontside probe pad in the frontside insulating layer and a backside probe pad in the backside insulating layer.

Abstract: The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor; and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.

Abstract: The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor; and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.

Abstract: The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor: and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.

Abstract: The present disclosure provides a semiconductor package, including at least two conductors and a first dielectric partially surrounding the at least two conductors, a capacitor substantially under the first dielectric, and a second dielectric over and lining along the first dielectric and top portions of the at least two conductors. The at least two conductors are respectively configured as an input/output (I/O) terminal of the semiconductor package. The capacitor includes a first electrode extending along a first direction and electrically connected with one of the at least two conductors, and a second electrode extending along a second direction opposite to the first direction and electrically connected to the other one of the at least two conductors. The second dielectric provides a compressive stress to the first dielectric. A method of forming the semiconductor package is also provided.

Abstract: The present disclosure provides a semiconductor package, including at least two conductors and a first dielectric partially surrounding the at least two conductors, a capacitor substantially under the first dielectric, and a second dielectric over and lining along the first dielectric and top portions of the at least two conductors. The at least two conductors are respectively configured as an input/output (I/O) terminal of the semiconductor package. The capacitor includes a first electrode extending along a first direction and electrically connected with one of the at least two conductors, and a second electrode extending along a second direction opposite to the first direction and electrically connected to the other one of the at least two conductors. The second dielectric provides a compressive stress to the first dielectric. A method of forming the semiconductor package is also provided.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Abstract: A fluorescent dye, a structure of a fluorescent storage media and method using thereof, are disclosed. The fluorescent dye of the present invention comprises an organic violet fluorescent compound having a chemical structure (I) is suitable for using a short wavelength laser having a wavelength less than 500 nm as an excitation source. When a short wavelength laser is used for exciting the organic violet fluorescent compound (I), a fluorescence having an emission wavelength larger than 500 nm is induced, and a reading signal can be provided by detecting the intensity of the fluorescence radiation.

Abstract: A system and method thereof for experiment management. A storage device stores an experiment plan record, a merge constraint and an integration rule. A processing unit configured to acquire a first experiment plan from the experiment plan record, and a second experiment plan. The processing unit generates an integrated experiment plan by merging the first experiment plan and the second experiment plan according to the merge constraint and the integration rule, and stores the integrated experiment plan to the storage device.

Abstract: A system and method thereof for experiment management. A storage device stores an experiment plan record, a merge constraint and an integration rule. A processing unit configured to acquire a first experiment plan from the experiment plan record, and a second experiment plan. The processing unit generates an integrated experiment plan by merging the first experiment plan and the second experiment plan according to the merge constraint and the integration rule, and stores the integrated experiment plan to the storage device.

Abstract: A polymeric material applicable for making a data-recording layer of a multi-layer recording medium in the process using a plastic stamper is provided. In the manufacturing process of multi-layer recording media, a plastic substrate carrying data signals is used as a stamper. The stamper includes a plastic substrate formed thereon a signal-carrying layer. The polymeric material is applied on the plastic stamper to form a data-recording layer. The polymeric material has good duplicating characteristics and has different adhesion to a metallic layer and a polymeric layer so that data-recording layer made by the polymeric material is easy to be peeled off from the stamper. The stamper is also reusable for several times so as to save manufacturing cost.

Abstract: A manufacturing method of cover layer of optical information storage media is disclosed. A plate and a substrate having a signal structure or recording layer are provided, a polymer resin is applied on the substrate. The plate is made to come in contact with the radiation-setting resin and then the radiation-setting resin is compressed against the substrate. The resulting structure is placed on a rotatable table and the rotatable is rotated. A radiation-setting resin layer with a uniform thickness is formed. The radiation-setting resin layer is illuminated by a UV light to harden the radiation-setting resin layer. Next, the plate is separed from the radiation-setting resin layer while the radiation-setting resin layer remain adhered to the substrate. The hardened radiation-setting resin layer serves as a cover layer.

Abstract: A production method of multi-layer information record carriers that involves forming a signal duplication layer on a substrate that contains signals, then replacing a metallic stamping plate with the substrate that comprises the signal duplication layer for manufacturing a signal layer of high molecular materials. After the signal layer has been subjected to curing by exposure to ultra violet light, the signal layer is separated from the signal duplication layer because of the difference between the adhesive forces of the different materials. Multi-layer information record carriers can be manufactured by repeating the manufacturing process. Since the manufacturing process of the invention is simple and speedy, it facilitates the creation of automated facilities for mass production.