Patents by Inventor Huey-Chi Chu
Huey-Chi Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9728597Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer.Type: GrantFiled: July 15, 2015Date of Patent: August 8, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsing-Lien Lin, Chia-Shiung Tsai, Cheng-Yuan Tsai, Huey-Chi Chu, Hai-Dang Trinh, Wen-Chuan Chiang, Wei-Min Tseng
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Patent number: 9425247Abstract: A metal insulator metal (MIM) capacitor includes a top electrode, a first via contacting a first surface of the top electrode, a bottom electrode, a second via contacting a second surface of the bottom electrode, and an insulator between the top electrode and the bottom electrode. One of the top and the bottom electrodes includes a first part and a second part. The first part has a first edge and a second edge opposing the first edge. The second part shares the second edge with the first part. At least a portion of the first edge contacts the respective via, and a first one of the first and the second edges is longer than a second one of the first and the second edges.Type: GrantFiled: November 2, 2015Date of Patent: August 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Jong Wang, Huey-Chi Chu, Kuo-Ji Chen, Ming-Hsiang Song, Wen-Chuan Chiang
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Patent number: 9391016Abstract: The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication.Type: GrantFiled: April 10, 2014Date of Patent: July 12, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Guo Shen, Wei-Min Tseng, Chien-Chung Wang, Huey-Chi Chu, Wen-Chuan Chiang
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Patent number: 9368392Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer.Type: GrantFiled: April 10, 2014Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Min Tseng, Shih-Guo Shen, Chien-Chung Wang, Huey-Chi Chu, Wen-Chuan Chiang
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Publication number: 20160163781Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer.Type: ApplicationFiled: July 15, 2015Publication date: June 9, 2016Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Hsing-Lien LIN, Chia-Shiung TSAI, Cheng-Yuan TSAI, Huey-Chi CHU, Hai-Dang TRINH, Wen-Chuan CHIANG, Wei-Min TSENG
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Publication number: 20160071920Abstract: A metal insulator metal (MIM) capacitor includes a top electrode, a first via contacting a first surface of the top electrode, a bottom electrode, a second via contacting a second surface of the bottom electrode, and an insulator between the top electrode and the bottom electrode. One of the top and the bottom electrodes includes a first part and a second part. The first part has a first edge and a second edge opposing the first edge. The second part shares the second edge with the first part. At least a portion of the first edge contacts the respective via, and a first one of the first and the second edges is longer than a second one of the first and the second edges.Type: ApplicationFiled: November 2, 2015Publication date: March 10, 2016Inventors: Chen-Jong Wang, Huey-Chi Chu, Kuo-Ji Chen, Ming-Hsiang Song, Wen-Chuan Chiang
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Patent number: 9219110Abstract: The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor.Type: GrantFiled: April 10, 2014Date of Patent: December 22, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Chung Wang, Wei-Min Tseng, Shih-Guo Shen, Huey-Chi Chu, Wen-Chuan Chiang
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Patent number: 9178008Abstract: Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.Type: GrantFiled: August 10, 2012Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ji Chen, Wen-Chuan Chiang, Huey-Chi Chu, Ming-Hsiang Song, Chen-Jong Wang
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Publication number: 20150295019Abstract: The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor.Type: ApplicationFiled: April 10, 2014Publication date: October 15, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Chung Wang, Wei-Min Tseng, Shih-Guo Shen, Huey-Chi Chu, Wen-Chuan Chiang
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Publication number: 20150294936Abstract: The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication.Type: ApplicationFiled: April 10, 2014Publication date: October 15, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Guo Shen, Wei-Min Tseng, Chien-Chung Wang, Huey-Chi Chu, Wen-Chuan Chiang
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Publication number: 20150295020Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer.Type: ApplicationFiled: April 10, 2014Publication date: October 15, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Min Tseng, Shih-Guo Shen, Chien-Chung Wang, Huey-Chi Chu, Wen-Chuan Chiang
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Publication number: 20140042590Abstract: Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.Type: ApplicationFiled: August 10, 2012Publication date: February 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Ji Chen, Wen-Chuan Chiang, Huey-Chi Chu, Ming-Hsiang Song, Chen-Jong Wang
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Patent number: 8436408Abstract: An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors.Type: GrantFiled: September 17, 2008Date of Patent: May 7, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chi Tu, Huey-Chi Chu, Kuo-Cheng Ching
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Publication number: 20100065944Abstract: An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors.Type: ApplicationFiled: September 17, 2008Publication date: March 18, 2010Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chi TU, Huey-Chi Chu, Kuo-Cheng Ching
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Patent number: 7115935Abstract: A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.Type: GrantFiled: April 9, 2004Date of Patent: October 3, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chi Tu, Chun-Yao Chen, Huey-Chi Chu
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Patent number: 6833578Abstract: A memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate extension passing over the capacitor. A spacer isolates an end of one of the capacitor electrodes from the transistor gate extension. In one embodiment, the spacer includes a first non-planar profile configured to engage a second non-planar profile comprising ends of the one of the capacitor electrodes and the insulating lining.Type: GrantFiled: December 11, 2003Date of Patent: December 21, 2004Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chi Tu, Chun-Yao Chen, Huey-Chi Chu, Chung-Wei Chang, Tien-Lu Lin, Kuo-Ching Huang, Wen-Cheng Chen, Tsung-Hsun Huang, Hsiao-Hui Tseng
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Publication number: 20040201053Abstract: A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.Type: ApplicationFiled: April 9, 2004Publication date: October 14, 2004Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Kuo-Chi Tu, Chun-Yao Chen, Huey-Chi Chu
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Patent number: 6720232Abstract: A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.Type: GrantFiled: April 10, 2003Date of Patent: April 13, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Kuo-Chi Tu, Chun-Yao Chen, Huey-Chi Chu
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Patent number: 6309968Abstract: The intrinsic refresh time of a DRAM and the reliability of the gate oxide of the pass transistor of the memory cell of the DRAM is improved by a method to form electronic components of an integrated circuit on a semiconductor substrate that will eliminate damage to molecular bonds and reduce junction leakage within the semiconductor substrate. The method begins by forming said electronic components using recognized methods to create implantations, insulating oxide layers, selectively etching the insulating oxide layers and deposited conductive layers to assemble the transistors and capacitors of the integrated circuit. Interconnections between the electronic components are then formed. The interconnections include multiple layers of metal, multiple layers of heavily doped polycrystalline silicon, and silicon/metal alloys to connect terminals of said electronic components to the multiple layers of metals and multiple layers of heavily doped polycrystalline silicon.Type: GrantFiled: September 7, 1999Date of Patent: October 30, 2001Assignee: Vanguard International Semiconductor CorporationInventors: Huey-Chi Chu, Yeh-Sen Lin
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Patent number: 6294435Abstract: By introducing a carefully controlled anneal step after the deposition of tungsten silicide (onto a layer of polysilicon) but before the deposition of a layer of silicon oxide, interaction between the tungsten silicide and a subsequently deposited layer of silicon oxide is greatly reduced or eliminated. This gives good values for the resistance of gate lines formed from the composite as well as for the contact resistance between the polysilicon and the tungsten silicide.Type: GrantFiled: October 8, 1999Date of Patent: September 25, 2001Assignee: Vanguard International Semiconductor CorporationInventors: Huey-Chi Chu, Jia-Ching Doong, Chung-Pin Yang