Abstract: A solar cell structure with a microsphere-roughened antireflection structure comprises a P-type metal contact electrode, a P-type semiconductor layer, a P-type monocrystalline substrate, an N-type semiconductor layer, an N-type metal contact electrode, and a microsphere-roughened antireflection layer. The N-type semiconductor layer and the P-type semiconductor layer are respectively arranged on an upper surface and a lower surface of the P-type monocrystalline substrate. The P-type metal contact electrode is arranged below the P-type semiconductor layer. The N-type metal contact electrode has a specified pattern and is connected with the N-type semiconductor layer. The microsphere-roughened antireflection layer is arranged on an upper surface of the N-type semiconductor layer without covering the N-type metal contact electrode. The microsphere-roughened antireflection layer reduces the reflection of sunlight and increases the transmittance of sunlight to enhance the efficiency of solar cells.

Abstract: A solar cell structure with a microsphere-roughened antireflection structure comprises a P-type metal contact electrode, a P-type semiconductor layer, a P-type monocrystalline substrate, an N-type semiconductor layer, an N-type metal contact electrode, and a microsphere-roughened antireflection layer. The N-type semiconductor layer and the P-type semiconductor layer are respectively arranged on an upper surface and a lower surface of the P-type monocrystalline substrate. The P-type metal contact electrode is arranged below the P-type semiconductor layer. The N-type metal contact electrode has a specified pattern and is connected with the N-type semiconductor layer. The microsphere-roughened antireflection layer is arranged on an upper surface of the N-type semiconductor layer without covering the N-type metal contact electrode. The microsphere-roughened antireflection layer reduces the reflection of sunlight and increases the transmittance of sunlight to enhance the efficiency of solar cells.

Abstract: A solar cell with an omnidirectional anti-reflection structure comprises a solar cell substrate, a transparent electric-conduction layer formed on one surface of the solar cell substrate, a plurality of microspheres formed on the transparent electric-conduction layer, and a dielectric layer. The microspheres have a diameter of 0.1-100 ?m. The dielectric layer is formed among the microspheres, and covers the surface of the transparent electric-conduction layer without the microspheres and has a thickness smaller than the diameter of the microspheres. Thus, the above-mentioned structure can enhance the absorption of the short-wavelength spectrum and increase the short-circuit current. Further, the structure with the microspheres is adaptable to the omnidirectional light absorption at various incident angles.

Abstract: A photo sense element that is composed of a P-type doped layer, a N-type doped layer, an intrinsic layer, a first electrode corresponding to the P-type doped layer, a second electrode corresponding to the N-type doped layer and a dielectric layer. Wherein, the intrinsic layer is disposed in between the P-type doped layer and the N-type doped layer to form a diode. Moreover, the dielectric layer is disposed in between the P-type doped layer and the first electrode or in between the N-type doped layer and the second electrode to form a dielectric layer capacitor. By using the appropriate circuit design to have the parasitic capacitor formed by the diodes under the reverse bias state in parallel with the dielectric layer capacitor, so the photo sense element has greater capacitance.

Abstract: Amorphous silicon/amorphous silicon germanium NI1PI2N position detectors are fabricated to suppress visible light and increase detection of infrared light. The material of I1 layer is amorphous silicon or amorphous silicon germanium used to absorb visible light, and material of I2 layer is amorphous silicon germanium or amorphous germanium used to absorb infrared light. A suppression of signal due to the absorption of the visible light and amplification of signals due to absorption of the infrared light can be obtained when the NI1P diode is forward biased and the P12N diode is reverse biased. The optical band gap of the I1 and I2 layers can be controlled by the Si/Ge atomic ratio. The suppression of visible light and enhanced detection of infrared light may be tuned by controlling thickness and optical band gaps of the I1 and I2 layers. The amorphous silicon and amorphous silicon germanium layers may be deposited by square-wave modulation at 13.56 MHz.

Abstract: A photodetector comprising a P-type, a N-type, an intrinsic layer, a first electrode corresponding to the P-type, a second electrode corresponding to the N-type, and a dielectric layer in such a way that the intrinsic layer is disposed between the P-type and the N-type for forming a diode and the dielectric layer is provided between the P-type and the first electrode (or between the N-type and the second electrode) for configuring a dielectric capacitor. By parallel connecting effective capacitor of reverse-biased diode and dielectric capacitor, the photodetector is capable of providing greatly increased capacitance. The operating modes involve charging the dielectric capacitor before subjecting the photodetector to photons for detecting signals.

Abstract: Amorphous silicon/amorphous silicon germanium NI1PI2N position detectors are fabricated to suppress visible light and increase detection of infrared light. The material of I1 layer is amorphous silicon or amorphous silicon germanium used to absorb visible light, and material of I2 layer is amorphous silicon germanium or amorphous germanium used to absorb infrared light. A suppression of signal due to the absorption of the visible light and amplification of signals due to absorption of the infrared light can be obtained when the NI1P diode is forward biased and the P12N diode is reverse biased. The optical band gap of the 11 and 12 layers can be controlled by the Si/Ge atomic ratio. The suppression of visible light and enhanced detection of infrared light may be tuned by controlling thickness and optical band gaps of the I1 and I2 layers. The amorphous silicon and amorphous silicon germanium layers may be deposited by square-wave modulation at 13.56 MHz.

Abstract: An ESD protection structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, will protect internal circuits formed on the semiconductor substrate from over stress due to excessively high voltages of an ESD voltage source. The ESD protection structure has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits. The ESD protection device has at least one source region that is the emitters of parasitic transistors connected to the reference voltage source and at least one drain region that is the collectors of the parasitic transistors connected to the junction of the input/output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source.

Abstract: An ESD protection structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, will protect internal circuits formed on the semiconductor substrate from over stress due to excessively high voltages of an ESD voltage source. The ESD protection structure has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits. The ESD protection device has at least one source region that is the emitters of parasitic transistors connected to the reference voltage source and at least one drain region that is the collectors of the parasitic transistors connected to the junction of the input/output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source.

Abstract: Methods are disclosed for depositing an in situ polysilicon layer on the back of a semiconductor wafer to reduce the temperature at the edge of the wafer during rapid thermal annealing (RTA). The reduced temperature results in decreased boron penetration at the edge of the wafer and a more uniform silicide resistance and threshold voltage across the wafer.