Patents by Inventor Huey Tzeng

Huey Tzeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250216883
    Abstract: An electronic device includes a gallium nitride (GaN) substrate having a GaN-based top layer attached to a silicon-based bottom layer, a bidirectional switch formed on the GaN-based top layer and including a first source node, a second source node and a common drain node, a first bias generator circuit arranged to couple the first source node to the silicon-based bottom layer, and a second bias generator circuit arranged to couple the second source node to the silicon-based bottom layer. In one aspect, when a voltage of the first source node is at a higher voltage than the second source node, the first bias generator circuit brings a voltage at the silicon-based bottom layer close to the voltage at the second source node.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Navitas Semiconductor Limited
    Inventors: Ren Huei Tzeng, Daniel M. Kinzer, Santosh Sharma
  • Patent number: 12211894
    Abstract: A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region. The active region includes a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region. The polysilicon resistor is formed above the drift region. The active region further includes a first charge balance region formed in the active region below the drift region.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: January 28, 2025
    Assignee: Silanna Asia Pte Ltd
    Inventors: Wen Cheng Lin, Ren Huei Tzeng, Shanghui Larry Tu
  • Publication number: 20240421813
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Application
    Filed: June 25, 2024
    Publication date: December 19, 2024
    Applicant: Navitas Semiconductor Limited
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Patent number: 12057824
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: August 6, 2024
    Assignee: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Publication number: 20240162288
    Abstract: A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region. The active region includes a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region. The polysilicon resistor is formed above the drift region. The active region further includes a first charge balance region formed in the active region below the drift region.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 16, 2024
    Applicant: Silanna Asia Pte Ltd
    Inventors: Wen Cheng Lin, Ren Huei Tzeng, Shanghui Larry Tu
  • Patent number: 11870429
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: January 9, 2024
    Assignee: Navitas Semiconductor Limited
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Patent number: 11869934
    Abstract: A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region. The active region includes a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region. The polysilicon resistor is formed above the drift region. The active region further includes a first charge balance region formed in the active region below the drift region.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: January 9, 2024
    Assignee: Silanna Asia Pte Ltd
    Inventors: Wen Cheng Lin, Ren Huei Tzeng, Shanghui Larry Tu
  • Patent number: 11694945
    Abstract: Disclosed is a device including a first finger of a plurality of lead fingers of a lead frame connected to a first flag. A second finger of the plurality of lead fingers of the lead frame is connected to a second flag. A semiconductor die is coupled to the lead frame. An encapsulant covers the semiconductor die, the lead frame, and a first end of the plurality of lead fingers, and excludes the first flag and the second flag. The first flag and the second flag are separated and electrically isolated from one another by the encapsulant.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: July 4, 2023
    Assignee: Silanna Asia Pte Ltd
    Inventors: Ariel Tan, Ren Huei Tzeng
  • Publication number: 20230112152
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 13, 2023
    Applicant: Navitas Semiconductor Limited
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Publication number: 20220416777
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 29, 2022
    Applicant: Navitas Semiconductor Limited
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Publication number: 20220189803
    Abstract: A process condition measurement apparatus is disclosed. The apparatus includes a substrate, one or more insulation portions, a first plurality of interconnect traces, a second plurality of interconnect traces, and a plurality of sensors disposed on the substrate. The second plurality of interconnect traces is disposed over the first plurality of interconnect traces and intersects at a plurality of locations to form a matrix of interconnect junctions across one or more locations of the substrate. A respective sensor is electrically coupled to a respective trace of the first and second plurality of interconnect traces. The respective sensor is individually readable by addressing the respective trace of the first and second plurality of interconnect traces.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 16, 2022
    Inventors: Farhat A. Quli, Andrew Nguyen, James Richard Bella, Earl Jensen, Huey Tzeng, Jing Zhou
  • Publication number: 20220045163
    Abstract: A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region. The active region includes a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region. The polysilicon resistor is formed above the drift region. The active region further includes a first charge balance region formed in the active region below the drift region.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 10, 2022
    Inventors: Wen Cheng Lin, Ren Huei Tzeng, Shanghui Larry Tu
  • Patent number: 11152864
    Abstract: An active clamp circuit for a power converter having a transformer includes a switch having a drain node, a gate node, and a source node, the drain node configured to be connected to a first terminal of a primary winding of the transformer, a capacitor having a first terminal connected to the source node, and a second terminal to be connected to a second terminal of the primary winding, a gate driver coupled to the gate node to control the switch and having a high-side input node and a low-side input node, the low-side input node being coupled to the first terminal of the capacitor, and a voltage regulator to: i) receive an input voltage from the second terminal of the capacitor, and ii) provide a regulated voltage to the high-side input node using the input voltage and being of a sufficient voltage level to control the switch.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: October 19, 2021
    Assignee: Silanna Asia Pte Ltd
    Inventor: Ren Huei Tzeng
  • Patent number: 11145282
    Abstract: The present invention relates to a novel woodwind mouthpiece, which comprises: a main body having an elongated streamlined shape; a hollow chamber and a bore inside the main body; a reed table on one side of the main body and partially suspended from the main body; a beak on an opposite side to the reed table on the main body; a reed rail surrounding the beak and connecting to two lateral sides of the reed table to form an opening window between a reed and the hollow chamber inside the main body; and a tip opening disposed between the reed rail at a tip of the beak and an virtual surface extending from a surface of the reed table, wherein the woodwind mouthpiece is made of a plastic, a metal, an alloy, a composite, wood or a combination thereof.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: October 12, 2021
    Inventor: Mien-Huei Tzeng
  • Publication number: 20210210418
    Abstract: Disclosed is a device including a first finger of a plurality of lead fingers of a lead frame connected to a first flag. A second finger of the plurality of lead fingers of the lead frame is connected to a second flag. A semiconductor die is coupled to the lead frame. An encapsulant covers the semiconductor die, the lead frame, and a first end of the plurality of lead fingers, and excludes the first flag and the second flag. The first flag and the second flag are separated and electrically isolated from one another by the encapsulant.
    Type: Application
    Filed: March 24, 2021
    Publication date: July 8, 2021
    Applicant: Silanna Asia Pte Ltd
    Inventors: Ariel Tan, Ren Huei Tzeng
  • Publication number: 20210193090
    Abstract: The present invention relates to a novel woodwind mouthpiece, which comprises: a main body having an elongated streamlined shape; a hollow chamber and a bore inside the main body; a reed table on one side of the main body and partially suspended from the main body; a beak on an opposite side to the reed table on the main body; a reed rail surrounding the beak and connecting to two lateral sides of the reed table to form an opening window between a reed and the hollow chamber inside the main body; and a tip opening disposed between the reed rail at a tip of the beak and an virtual surface extending from a surface of the reed table, wherein the woodwind mouthpiece is made of a plastic, a metal, an alloy, a composite, wood or a combination thereof.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 24, 2021
    Inventor: Mien-Huei TZENG
  • Patent number: 10971434
    Abstract: Disclosed is a device including a lead frame having a body with a top surface and a bottom surface and lead fingers. Each lead finger has a first end and a second end. A semiconductor die is coupled to the body. A first flag is a first exposed portion of the body and integral with the first end of a first lead finger. The first flag and the first lead finger are a continuous material. A second flag is a second exposed portion of the body and integral with the first end of a second lead finger. The second flag and the second lead finger are a continuous material. An encapsulant covers the die, the bottom surface of the body, the first end of the lead fingers and a portion of the top surface of the body. The flags are separated and electrically isolated from one another by the encapsulant.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 6, 2021
    Assignee: Silanna Asia Pte Ltd
    Inventors: Ariel Tan, Ren Huei Tzeng
  • Publication number: 20200350825
    Abstract: An active clamp circuit for a power converter having a transformer includes a switch having a drain node, a gate node, and a source node, the drain node configured to be connected to a first terminal of a primary winding of the transformer, a capacitor having a first terminal connected to the source node, and a second terminal to be connected to a second terminal of the primary winding, a gate driver coupled to the gate node to control the switch and having a high-side input node and a low-side input node, the low-side input node being coupled to the first terminal of the capacitor, and a voltage regulator to: i) receive an input voltage from the second terminal of the capacitor, and ii) provide a regulated voltage to the high-side input node using the input voltage and being of a sufficient voltage level to control the switch.
    Type: Application
    Filed: June 1, 2020
    Publication date: November 5, 2020
    Applicant: Silanna Asia Pte Ltd
    Inventor: Ren Huei Tzeng
  • Patent number: D926869
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 3, 2021
    Inventor: Mien-Huei Tzeng
  • Patent number: D938514
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: December 14, 2021
    Inventor: Mien-Huei Tzeng