Abstract: An integrated circuit is provided and includes first and second gates arranged in first and second layers, wherein the first and second gates extend in a first direction; a first insulating layer interposed between the first and second gates, wherein the first insulating layer, a first portion of the first gate, and a first portion of the second gate overlap with each other in a layout view; a cut layer, different from the first insulating layer, disposed on a second portion of the first gate; a first via passing through the cut layer and coupled to the second portion of the first gate; and a second via overlapping the first portion of the first gate and the first portion of the second gate, and coupled to the second gate. The first and second vias are configured to transmit different control signals to the first and second gates.

Abstract: An integrated circuit includes first-type transistors aligned within a first-type active zone, second-type transistors aligned within a second-type active zone, a first power rail and a second power rail extending in a first direction. A first distance between the long edge of the first power rail and the first alignment boundary of the first-type active zone is different from a second distance between the long edge of the second power rail and the first alignment boundary of the second-type active zone. Each of the first distance and the second distance is along a second direction which is perpendicular to the first direction.

Abstract: A power conversion system includes: first and second switches, a switching power converter, a battery switch and a conversion control circuit. In an external power mode, the first and second switches are controlled to generate an intermediate power from a first power and generate a second power from the intermediate power for powering an external load. In a battery power mode, the conversion control circuit controls the battery switch, the switching power converter and the second switch to generate a system power from a battery power, convert the system power to generate the intermediate power and generate the second power from the intermediate power. In the external power mode, the switching power converter is controlled to enter the battery power mode when the intermediate voltage is reduced to a transient state threshold, wherein a minimum voltage level of the intermediate power is close to a minimum voltage regulation level.

Abstract: A method is provided and includes operations below: forming a multilayer stack, wherein the multilayer stack includes multiple first semiconductor layers and multiple second semiconductor layers that are alternately stacked; forming a first source region and a first drain region on opposing sides of a first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack; removing the second semiconductor layers in the multilayer stack; forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack; forming a first insulating layer above the first gate region; and forming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack.

Abstract: A semiconductor device includes a semiconductor substrate with active regions and a first buried metal layer provided below the semiconductor substrate. The first buried metal layer includes a first buried conductive rail, a first set of buried conductive fingers that extends from the first buried conductive rail, and a second set of buried conductive fingers that are interleaved with the first set of buried conductive fingers. The first set and the second set of buried conductive fingers extends beneath more than one of the active regions. In this manner, the first set and the second set of buried conductive fingers can be utilized to distribute different voltages, such as an ungated reference voltage TVDD and a gated reference voltage VVDD in a header circuit with reduced resistance.

Abstract: A combination of probiotics for improving body compositions includes Lacticaseibacillus paracasei S38 and Bacillus coagulans BC198. The combination of probiotics can be a medicine composition, a nutrient supplement, healthy food or a combination thereof. The applications of the combination of probiotics include weight loss, reduction of fat, abatement of appetite, production of butyric acid within intestinal tracts and an increased count of Akkermansia muciniphila or Ruminococcaceae inside intestines.

Abstract: An integrated circuit includes a first and second conductor, and a first and second pair of transistors. The first conductor is on a back-side of a substrate, extending in a first direction, and being configured to supply a first supply voltage. The second conductor is on the back-side of the substrate, and extending in the first direction. The first pair of transistors includes a first gate extending in a second direction, overlapping at least the second conductor, being located on a first level of a front-side of the substrate opposite from the back-side. The second pair of transistors includes a second gate extending in the second direction, overlapping at least the second conductor, being on the first level, and being separated from the first gate in the first direction. The second conductor electrically couples the first gate and the second gate together.

Abstract: An IC device includes a gate electrode extending along a first direction, a channel extending through the gate electrode in a second direction perpendicular to the first direction and positioned at a first elevation along a third direction perpendicular to each to the first and second directions, an isolation layer positioned within the gate electrode at a second elevation different from the first elevation, first and second source/drain (S/D) structures adjacent to the channel and positioned on opposite sides of the gate electrode at the first elevation, third and fourth S/D structures positioned on opposite sides of the gate electrode at the second elevation, and a conductive structure extending in the second direction and electrically connected to each of the third and fourth S/D structures.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

Abstract: A power conversion system includes: first and second switches, a switching power converter, a battery switch and a conversion control circuit. In an external power mode, the first and second switches are controlled to generate an intermediate power from a first power and generate a second power from the intermediate power for powering an external load. In a battery power mode, the conversion control circuit controls the battery switch, the switching power converter and the second switch to generate a system power from a battery power, convert the system power to generate the intermediate power and generate the second power from the intermediate power. In the external power mode, the switching power converter is controlled to enter the battery power mode when the intermediate voltage is reduced to a transient state threshold, wherein a minimum voltage level of the intermediate power is close to a minimum voltage regulation level.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure extending and a second-type active-region semiconductor structure both extending in a first direction. The second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device still includes a front-side power rail extending in the second direction in the front-side conductive layer and a back-side power rail extending in the second direction in the back-side conductive layer. The integrated circuit device further includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Abstract: A harmonic deceleration module, a dynamic power device, an automatic mobile vehicle, a transfer apparatus, a dynamic power supply system, and an electric bicycle are provided. The harmonic deceleration module includes a connecting member, a flexible bearing, a first frame, a first circular spline, a second frame, and a second circular spline. When the connecting member is driven, the connecting member rotates around a central axis. The connecting member has a cam part, and the cam part and the flexible bearing jointly form a wave generator. The wave generator is configured to be driven by the connecting member to drive a flexspline to continually and flexibly deform, and the flexspline drives the second circular spline and the second frame connected to the second circular spline to rotate. The second frame has a hollow channel penetrating through the second frame along the central axis.

Abstract: An IC structure includes first and second complementary field-effect transistors (CFETs) positioned in a semiconductor wafer, each of the first and second CFETs including a gate structure extending in a first direction, an n-type channel extending through the gate structure in a second direction perpendicular to the first direction, and a p-type channel extending through the gate structure in the second direction and aligned with the n-type channel in a third direction perpendicular to each of the first and second directions. A metal line extends in the first direction, is aligned with each of the first and second CFETs in the third direction, and is configured to distribute a power supply or reference voltage to each of the first and second CFETs. The metal line is a metal line closest to each of the first and second CFETs along the third direction and extending in the first direction.

Abstract: An integrated circuit includes a first power rail, a conductive structure, a first active region of a first set of transistors and a second active region of a second set of transistors. The first power rail is on a back-side of a substrate, extends in a first direction, and is configured to supply a first supply voltage. The first active region extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side. The second active region extends in the first direction, is on the first level of the front-side of the substrate, and is separated from the first active region in a second direction different from the first direction. The conductive structure is on the back-side of the substrate, extends in the first direction, and is electrically coupled to the first active region and the second active region.

Abstract: A method of generating an IC layout diagram includes overlapping a channel region of an upper transistor of a complementary field-effect transistor (CFET) in an IC layout with a gate region of the CFET, thereby defining a channel overlap region, positioning an isolation region in the IC layout, the isolation region including an entirety of the channel overlap region, intersecting the isolation region with a conductive region, and generating an IC layout diagram based on the IC layout.

Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

Abstract: A method includes fabricating a first-voltage underlayer power rail conductively connecting to the source region of a first-type transistor and fabricating a second-voltage underlayer power rail conductively connecting to the source region of a second-type transistor. Each of the first-voltage and second-voltage underlayer power rails extends in a first direction. The method also includes patterning a first connection layer to form a first-voltage power rail and a second-voltage power rail extending in the second direction which is perpendicular to the first direction. The first-voltage power rail is directly connected with the first-voltage underlayer power rail through a first via-connector and the second-voltage power rail is directly connected with the second-voltage underlayer power rail through a second via-connector.

Abstract: An integrated circuit includes metal rails. The integrated circuit includes a first layer including a first metal rail and a second layer including a second metal rail, where the second layer is above the first layer along a first direction. The integrated circuit includes a third layer including an active region of a transistor, where the third layer is above the second layer along the first direction. The integrated circuit includes a fourth layer including a third metal rail, where the fourth layer is above the third layer along the first direction. The integrated circuit includes a fifth layer including a fourth metal rail, where the fifth layer is above the fourth layer along the first direction.