Abstract: Global register protection in a multi-threaded processor is described. In an embodiment, global resources within a multi-threaded processor are protected by performing checks, before allowing a thread to write to a global resource, to determine whether the thread has write access to the particular global resource. The check involves accessing one or more local control registers or a global control field within the multi-threaded processor and in an example, a local register associated with each other thread in the multi-threaded processor is accessed and checked to see whether it contains an identifier for the particular global resource. Only if none of the accessed local resources contain such an identifier, is the instruction issued and the thread allowed to write to the global resource. Otherwise, the instruction is blocked and an exception may be raised to alert the program that issued the instruction that the write failed.

Abstract: Soft-partitioning of a register file cache is implemented by renaming registers associated with an instruction based on which thread, in a multi-threaded out-of-order processor, the instruction belongs to. The register renaming may be performed by a register renaming module and in an embodiment, the register renaming module receives an instruction for register renaming which identifies the thread associated with the instruction and one or more architectural registers. Available physical registers are then allocated to each identified architectural register based on the identified thread. In some examples, the physical registers in the multi-threaded out-of order processor are logically divided into groups and physical registers are allocated based on a thread to group mapping. In further examples, the thread to group mapping is not fixed but may be updated based on the activity level of one or more threads in the multi-threaded out-of-order processor.

Abstract: Methods and reservation stations for selecting instructions to issue to a functional unit of an out-of-order processor. The method includes classifying each instruction into one of a number of categories based on the type of instruction. Once classified an instruction is stored in an instruction queue corresponding to the category in which it was classified. Instructions are then selected from one or more of the instruction queues to issue to the functional unit based on a relative priority of the plurality of types of instructions. This allows certain types of instructions (e.g. control transfer instructions, flag setting instructions and/or address generation instructions) to be prioritized over other types of instructions even if they are younger.

Abstract: Global register protection in a multi-threaded processor is described. In an embodiment, global resources within a multi-threaded processor are protected by performing checks, before allowing a thread to write to a global resource, to determine whether the thread has write access to the particular global resource. The check involves accessing one or more local control registers or a global control field within the multi-threaded processor and in an example, a local register associated with each other thread in the multi-threaded processor is accessed and checked to see whether it contains an identifier for the particular global resource. Only if none of the accessed local resources contain such an identifier, is the instruction issued and the thread allowed to write to the global resource. Otherwise, the instruction is blocked and an exception may be raised to alert the program that issued the instruction that the write failed.

Abstract: Methods of increasing the efficiency of memory resources within a processor are described. In an embodiment, instead of including dedicated DSP indirect register resource for storing data associated with DSP instructions, this data is stored in an allocated and locked region within the cache. The state of any cache lines which are used to store DSP data is then set to prevent the data from being written to memory. The size of the allocated region within the cache may vary according to the amount of DSP data that needs to be stored and when no DSP instructions are being run, no cache resources are allocated for storage of DSP data.

Abstract: Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.

Abstract: An improved mechanism for copying data in memory is described which uses aliasing. In an embodiment, data is accessed from a first location in a memory and stored in a cache line associated with a second, different location in the memory. In response to a subsequent request for data from the second location in the memory, the cache returns the data stored in the cache line associated with the second location in the memory. The method may be implemented using additional hardware logic in the cache which is arranged to receive an aliasing request from a processor which identifies both the first and second locations in memory and triggers the accessing of data from the first location for storing in a cache line associated with the second location.

Abstract: A method and load and store buffer for issuing a load instruction to a data cache. The method includes determining whether there are any unresolved store instructions in the store buffer that are older than the load instruction. If there is at least one unresolved store instruction in the store buffer older than the load instruction, it is determined whether the oldest unresolved store instruction in the store buffer is within a speculation window for the load instruction. If the oldest unresolved store instruction is within the speculation window for the load instruction, the load instruction is speculatively issued to the data cache. Otherwise, the load instruction is stalled until any unresolved store instructions outside the speculation window are resolved. The speculation window is a short window that defines a number of instructions or store instructions that immediately precede the load instruction.

Abstract: Register files for use in an out-of-order processor that have been divided into a plurality of sub-register files. The register files also have a plurality of buffers which are each associated with one of the sub-register files. Each buffer receives and stores write operations destined for the associated sub-register file which can be later issued to the sub-register file. Specifically, each clock cycle it is determined whether there is at least one write operation in the buffer that has not been issued to the associated sub-register file. If there is at least one write operation in the buffer that has not been issued to the associated sub-register file, one of the non-issued write operations is issued to the associated sub-register file.

Abstract: Methods and circuits for controlling an automatic gain control (AGC) circuit wherein the AGC circuit is used to adjust the gain of a signal input to an analog to digital converter. The method includes obtaining a plurality of samples from the output of the analog to digital converter and determining whether the amplitude of each sample is greater than a threshold amplitude value. If the amplitude of a sample is greater than the threshold amplitude value then a counter value is incremented. The target average amplitude of the automatic gain control circuit is then periodically adjusted based on the counter value.

Abstract: Methods and branch predictors for predicting a target location of a jump table switch statement in a program. The method includes continuously monitoring instructions at the branch predictor to determine if they write to registers used to store an input variable to a jump table switch statement. Any update to a monitored register is stored in a register table maintained by the branch predictor. Then when it comes time to make a prediction for a jump table switch statement instruction the branch predictor uses the register value stored in the table is used to predict where the jump table switch statement will branch to.

Abstract: Methods and apparatus for dynamically resizing circular buffers are described wherein circular buffers are dynamically allocated arrays from a pool of arrays. The method comprises receiving either a request to add data to a circular buffer or to remove data from a circular buffer. If the request is an addition request and the circular buffer is full, an array from the pool is allocated to the circular buffer. If, however, the request is a removal request and removal of the data creates an empty array, an array is de-allocated from the circular buffer and returned to the pool. Any arrays that are not allocated to a circular buffer may be disabled to conserve power.

Abstract: Global register protection in a multi-threaded processor is described. In an embodiment, global resources within a multi-threaded processor are protected by performing checks, before allowing a thread to write to a global resource, to determine whether the thread has write access to the particular global resource. The check involves accessing one or more local control registers or a global control field within the multi-threaded processor and in an example, a local register associated with each other thread in the multi-threaded processor is accessed and checked to see whether it contains an identifier for the particular global resource. Only if none of the accessed local resources contain such an identifier, is the instruction issued and the thread allowed to write to the global resource. Otherwise, the instruction is blocked and an exception may be raised to alert the program that issued the instruction that the write failed.

Abstract: Multi-stage register renaming using dependency removal is described. In an embodiment, the registers are renamed in two stages. The first stage involves removing all the dependencies within a set of instructions which are being renamed together. The final stage then renames all registers in parallel using a renaming map. In various embodiments, the dependencies are removed in the first stage using a fixed mapping to rename destination registers in each instruction and in some embodiments the fixed mapping is based on the position of a destination register within the set of instructions. Dependent registers, which are those registers which are read in an instruction but have been written in a previous instruction in the set, are also renamed in the first stage. In addition to performing the renaming in the final stage, the renaming map is updated.

Abstract: A technique for restoring a register renaming map is described. In one example, a restore table having a number of storage locations saves a copy of the register renaming map whenever a flow-risk instruction is passed to a re-order buffer. When all storage locations are full, further instructions still pass to the re-order buffer, but a copy of the map is not saved. A storage location subsequently becomes available when its associated flow-risk instruction is executed. A register renaming map state for an unrecorded flow-risk instruction passed to the re-order buffer whilst the storage locations were full is generated and stored in the available location. This is generated using the restore table entry for a previous flow-risk instruction and re-order buffer values for intervening instructions between the previous and unrecorded flow-risk instructions. The restore table can be used to restore the map if an unexpected change in instruction flow occurs.

Abstract: Described is a plenum, in particular the air plenum of a gas-turbine combustion chamber, having at least two flow inlets, for introducing gas flows into the plenum, in which the gas flows are guided essentially along the inner wall of the plenum and are directed toward one another in such a way that the gas flows, after coinciding, are directed as a free gas flow away from the inner wall.The invention is distinguished by the fact that at least one flow obstacle (11) oriented in interaction with the direction of flow of the gas flows (1, 2) guided on the inner wall (3) is provided on the inner wall (3).