Abstract: A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.

Abstract: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in rows and columns. A row of ferroelectric memory cells includes a common wordline that allows access to the memory cells of the row and also includes at least two platelines associated with the row. At least one of the at least two platelines is associated with adjacent columns of ferroelectric memory cells within the row. The row of ferroelectric memory cells includes another word line which is not associated with the at least two platelines. Other methods and systems are also disclosed.

Abstract: A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each read operation. A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each write operation. A process of operating an integrated circuit containing a programmable data storage component including four data ferroelectric capacitors, in which power is removed from a state circuit after each read operation and after each write operation.

Abstract: A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.

Abstract: A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes adjusting a disturb voltage and determining if a screening data value and a read data value meet a criterion for determining a limiting disturb voltage.

Abstract: A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each read operation. A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each write operation. A process of operating an integrated circuit containing a programmable data storage component including four data ferroelectric capacitors, in which power is removed from a state circuit after each read operation and after each write operation.

Abstract: A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.

Abstract: A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.

Abstract: Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

Abstract: A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.

Abstract: A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.

Abstract: A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes adjusting a disturb voltage and determining if a screening data value and a read data value meet a criterion for determining a limiting disturb voltage.

Abstract: An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.

Abstract: One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.

Abstract: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in rows and columns. A row of ferroelectric memory cells includes a common wordline that allows access to the memory cells of the row and also includes at least two platelines associated with the row. At least one of the at least two platelines is associated with adjacent columns of ferroelectric memory cells within the row. The row of ferroelectric memory cells includes another word line which is not associated with the at least two platelines. Other methods and systems are also disclosed.

Abstract: A memory cell for storing a charge that gives rise to a cell voltage representing a bit value, the memory cell being capable of having the cell voltage boosted to a boost value at a time following reading of the stored charge. The memory cell includes a first capacitor connected between a first node and ground. A second capacitor is connected between a second node and ground, and a first switch is connected between the first node and the second node. A second switch and a third capacitor are connected in series between the first node and the second node, with a terminal of the second switch being connected to the first node, the common connection node of the second switch and the third capacitor comprising a third node. A third switch is connected between the third node and ground. In operation, in a first storage phase the first and third switches are closed and the second switch is open.

Abstract: One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.

Abstract: Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

Abstract: Methods (200) and systems (108) are provided for reading data from ferroelectric memory cells (106) in which charge is removed from a sense amp input (SABL/SABLB) prior to application of a plateline signal (PL) to the target cell capacitor (CFE). Where the sense amp input (SABL/SABLB) is initially precharged to zero volts, the extraction of charge provides a negative voltage on the data bitline (BL/BLB) when the plateline signal (PL) is applied, allowing adequate voltage to be applied across the cell capacitor (CFE) together with reduced plateline voltages (PL).

Abstract: An integrated circuit (IC) chip contains a small non-volatile “ID” memory such as an FeRAM array that stores information associated with manufacturing, testing, and performance of the IC chip. The stored information can include but is not limited to a serial number, a wafer ID, a batch ID, a date code, chip history, test data, and performance information. The storing information on the chip eliminates any difficulty in matching the information with the IC chip and provides a flexible permanent record of any information the manufacturer may find useful. The ID memory thus permits tracking and identification of ICs to a degree that was not previously practical. Additionally, a self-test can compare prior test results stored in the ID memory to current self-test results to detect defects or to select operating parameters of the integrated circuit.