Abstract: A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.

Abstract: A statement in at least one hardware definition language (HDL) file specifies a plurality of design entities representing a functional portion of a digital system. The plurality of design entities have an associated plurality of configuration latches each having a plurality of different possible latch values, where different sets of latch values for the plurality of configuration latches correspond to different configurations of the functional portion of the digital system. With a statement in the at least one HDL file, a Dial group entity is associated with one of the plurality of design entities. The Dial group entity has a Dial list listing a plurality of Dial entities whose settings collectively control which set of latch values is loaded into the plurality of configuration latches. Membership in the Dial group constrains all instances of the plurality of Dial entities belonging to a particular instance of the Dial group to be set as a group.

Abstract: A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather to the entry. When a new gather does not occur before the counter reaches a threshold saturation point, the entry is signaled ready for dispatch. By defining an optimum threshold saturation point before the counter expires, sufficient time is provided for the entry to gather a proximate-in-time store operation. The entry may be deemed eligible for selection when certain conditions occur, including the entry becoming full, issuance of a barrier operation, and saturation of the counter. The use of the counter increases the ability of a store queue entry to complete gathering of enough store operations to update an entire cache line before that entry is dispatched to an RC machine.

Abstract: A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.

Abstract: A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store operations while the store queue full signal is asserted. A copy of the speculatively issued store operation is placed within a speculative store buffer. The core waits for a signal from the store queue indicating the store operation was accepted into the store queue. When the speculatively-issued store operation is accepted within the store queue, the copy is discarded from the buffer. However, when the store operation is rejected, the speculative store logic re-issues the store operation ahead of normal store operations.

Abstract: A statement in at least one hardware definition language (HDL) file specifies a plurality of design entities representing a functional portion of a digital system. The plurality of design entities have an associated plurality of configuration latches each having a plurality of different possible latch values, where different sets of latch values for the plurality of configuration latches correspond to different configurations of the functional portion of the digital system. With a statement in the at least one HDL file, a Dial group entity is associated with one of the plurality of design entities. The Dial group entity has a Dial list listing a plurality of Dial entities whose settings collectively control which set of latch values is loaded into the plurality of configuration latches. Membership in the Dial group constrains all instances of the plurality of Dial entities belonging to a particular instance of the Dial group to be set as a group.