Abstract: A multiprocessor data processing system includes a processor core having a translation structure for buffering a plurality of translation entries. The processor core receives a sequence of a plurality of translation invalidation requests. In response to receipt of each of the plurality of translation invalidation requests, the processor core determines that each of the plurality of translation invalidation requests indicates that it does not require draining of memory referent instructions for which address translation has been performed by reference to a respective one of a plurality of translation entries to be invalidated. Based on the determination, the processor core invalidates the plurality of translation entries in the translation structure without regard to draining from the processor core of memory access requests for which address translation was performed by reference to the plurality of translation entries.

Abstract: A data processing system includes a plurality of processor cores each having a respective associated cache memory, a memory controller, and a system memory coupled to the memory controller. A zero request of a processor core among the plurality of processor cores is transmitted on an interconnect fabric of the data processing system. The zero request specifies a target address of a target memory block to be zeroed has no associated data payload. The memory controller receives the zero request on the interconnect fabric and services the zero request by zeroing in the system memory the target memory block identified by the target address, such the target memory block is zeroed without caching the zeroed target memory block in the cache memory of the processor core.

Abstract: A data processing system includes multiple processing units all having access to a shared memory. A processing unit of the data processing system includes a processor core including an upper level cache, core reservation logic that records addresses in the shared memory for which the processor core has obtained reservations, and an execution unit that executes memory access instructions including a fronting load instruction. Execution of the fronting load instruction generates a load request that specifies a load target address. The processing unit further includes lower level cache that, responsive to receipt of the load request and based on the load request indicating an address match for the load target address in the core reservation logic, protects the load target address against access by any conflicting memory access request during a protection interval following servicing of the load request.

Abstract: A multiprocessor data processing system includes a processor core having a translation structure for buffering a plurality of translation entries. In response to receipt of a translation invalidation request, the processor core determines from the translation invalidation request that the translation invalidation request does not require draining of memory referent instructions for which address translation has been performed by reference to a translation entry to be invalidated. Based on the determination, the processor core invalidates the translation entry in the translation structure and confirms completion of invalidation of the translation entry without regard to draining from the processor core of memory access requests for which address translation was performed by reference to the translation entry.

Abstract: A data processing system includes a processor core having a shared store-through upper level cache and a store-in lower level cache. The processor core executes a plurality of simultaneous hardware threads of execution including at least a first thread and a second thread, and the shared store-through upper level cache stores a first cache line accessible to both the first thread and the second thread. The processor core executes in the first thread a store instruction that generates a store request specifying a target address of a storage location corresponding to the first cache line. Based on the target address hitting in the shared store-through upper level cache, the first cache line is temporarily marked, in the shared store-through upper level cache, as private to the first thread, such that any memory access request by the second thread targeting the storage location will miss in the shared store-through upper level cache.

Abstract: A processing unit for a data processing system includes a cache memory having reservation logic and a processor core coupled to the cache memory. The processor includes an execution unit that executes instructions in a plurality of concurrent hardware threads of execution including at least first and second hardware threads. The instructions include, within the first hardware thread, a first load-reserve instruction that identifies a target address for which a reservation is requested. The processor core additionally includes a load unit that records the target address of the first load-reserve instruction and that, responsive to detecting, in the second hardware thread, a second load-reserve instruction identifying the target address recorded by the load unit, blocks the second load-reserve instruction from establishing a reservation for the target address in the reservation logic.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Abstract: In a data processing system, a processor creating level qualifying logic within instrumentation of a hardware description language (HDL) simulation model of a design. The level qualifying logic is configured to generate a first event of a first type for a first simulation level and to generate a second event of second type for a second simulation level. The processor simulates the design utilizing the HDL simulation model, where the simulation includes generating the first event of the first type responsive to the simulating being performed at the first simulation level and generating the second event of the second type responsive to the simulating being performed at the second simulation level. Responsive to the simulating, the processor records, within data storage, at least one occurrence of an event from a set including the first event and the second event.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Abstract: In a processing unit, a processor core executes instructions in a plurality of simultaneous hardware threads, where multiple of the plurality of hardware threads concurrently execute memory transactions. A transactional memory circuit in the processing unit tracks transaction footprints of the memory transactions of the multiple hardware thread. In response to detecting failure of a given memory transaction of one of the plurality of multiple threads due to an overflow condition, the transactional memory circuit transitions to a throttled operating mode and reduces a number of hardware threads permitted to concurrently execute memory transactions.

Abstract: A data processing system includes multiple processing units all having access to a shared memory. A processing unit includes a processor core that executes memory access instructions including a store-conditional instruction that generates a store-conditional request specifying a store target address and store data. The processing unit further includes a reservation register that records shared memory addresses for which the processor core has obtained reservations and a cache that services the store-conditional request by conditionally updating the shared memory with the store data based on the reservation register indicating a reservation for the store target address. The processing unit additional includes a blocking state machine configured to protect the store target address against access by any conflicting memory access request during a protection window extension following servicing of the store-conditional request.

Abstract: A data processing system includes multiple processing units all having access to a shared memory. A processing unit includes a processor core that executes memory access instructions including a fronting load instruction, wherein execution of the fronting load instruction generates a load request that specifies a load target address. The processing unit also includes reservation logic that records addresses in the shared memory for which the processor core has obtained reservations. In addition, the processing unit includes a read-claim state machine that, responsive to receipt of the load request and based on an address match for the load target address in the reservation logic, protects the load target address against access by any conflicting memory access request during a protection interval following servicing of the load request.

Abstract: Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.

Abstract: A data processing system includes a plurality of processor cores each having a respective store-through upper level cache and a store-in banked lower level cache. Store requests of the plurality of processor cores destined for the banked lower level cache are buffered in multiple store queues including a first store queue and a second store queue. In response to determining that the multiple store queues contain store requests targeting a common bank of the banked lower level cache, store requests from the first store queue are temporarily favored for selection for issuance to the banked lower level cache over those in the second store queue.

Abstract: A data processing system includes a plurality of processor cores each having a respective store-through upper level cache and a store-in banked lower level cache. Store requests of the plurality of processor cores destined for the banked lower level cache are buffered in multiple store queues including a first store queue and a second store queue. In response to determining that the multiple store queues contain store requests targeting a common bank of the banked lower level cache, store requests from the first store queue are temporarily favored for selection for issuance to the banked lower level cache over those in the second store queue.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Abstract: Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.

Abstract: A technique for operating a lower level cache memory of a data processing system includes receiving an operation that is associated with a first thread. Logical partition (LPAR) information for the operation is used to limit dependencies in a dependency data structure of a store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.