Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.

Abstract: A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.

Abstract: A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.

Abstract: A cladding clip comprising a lateral base, a head coupled to the lateral base, and a flexible lip upstanding from the lateral base and laterally spaced from the neck along the base is disclosed. The flexible lip is hooked so that a lateral part of the lip extends laterally spaced from the base.

Abstract: A password and/or email address management platform configured to regenerate a previously generated password for a given web domain or digital system without permanently storing the previously generated password. The platform can operate without maintaining a permanent store or list of other user-related information, e.g. a list of web domains or systems for which passwords have been generated. In an embodiment, the platform performs the steps of concatenating a plurality of password input data elements into a requested phantom password input data string, applying a hashing algorithm to the requested phantom password input data string to generate a phantom password hash, applying a hash-to-string function to convert the phantom password hash to a phantom password, and purging the password generation system of the phantom password after it is notified to a user.

Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

Abstract: A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period.

Abstract: A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.

Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.

Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

Abstract: A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.

Abstract: An integrated circuit structure includes a first conductive layer (MET4) including a first forked conductive structure (310), an insulating layer (320, ILD45) substantially disposed over the first forked conductive structure (310), a plurality of conductive vias (331-334) through the insulating layer (ILD45) and electrically connecting with the first forked conductive structure (310), and a second conductive layer (MET5) including a second forked conductive structure (340) substantially disposed over at least a portion of the insulating layer (ILD45) and generally perpendicular to the first forked conductive structure (310), the plurality of conductive vias (331-334) electrically connecting with the second forked conductive structure (340). Other structures, devices, and processes are also disclosed.

Abstract: An integrated circuit structure includes a first conductive layer (MET4) including a first forked conductive structure (310), an insulating layer (320, ILD45) substantially disposed over the first forked conductive structure (310), a plurality of conductive vias (331-334) through the insulating layer (ILD45) and electrically connecting with the first forked conductive structure (310), and a second conductive layer (MET5) including a second forked conductive structure (340) substantially disposed over at least a portion of the insulating layer (ILD45) and generally perpendicular to the first forked conductive structure (310), the plurality of conductive vias (331-334) electrically connecting with the second forked conductive structure (340). Other structures, devices, and processes are also disclosed.

Abstract: An integrated circuit structure includes a first conductive layer (MET4) including a first forked conductive structure (310), an insulating layer (320, ILD45) substantially disposed over the first forked conductive structure (310), a plurality of conductive vias (331-334) through the insulating layer (ILD45) and electrically connecting with the first forked conductive structure (310), and a second conductive layer (MET5) including a second forked conductive structure (340) substantially disposed over at least a portion of the insulating layer (ILD45) and generally perpendicular to the first forked conductive structure (310), the plurality of conductive vias (331-334) electrically connecting with the second forked conductive structure (340). Other structures, devices, and processes are also disclosed.

Abstract: A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period.

Abstract: Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input clock and a second input clock are generated with the second input clock having a phase that is programmably shifted relative to the first input clock when the system is operating at a lowered operating voltage or different temperature, for example. The first and second input clocks are coupled to a dually clocked flip flop, each having a primary latch and a secondary latch. A composite clock signal is generated in response to the first input clock and the second input clock. For example, a first signal is latched in the primary latch in response to the composite clock signal and a second signal is latched in the secondary latch in response to the first input clock signal.

Abstract: A HDMI (High-Definition Multimedia Interface) transmitter component may be operated solely on power that is scavenged and converted from termination tail current received while the HDMI transmitter component is coupled to an HDMI compliant sink connector on a HDMI receiver component. The termination tail current is received at the transmitter component from a plurality of differential HDMI signals from terminators on a receiver component. A portion of the received tail current is converted to form a supply voltage Vdd source. Function logic on the transmitter component is operated using the Vdd voltage, and the function logic is configured to control the plurality of differential signals.

Abstract: Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input clock and a second input clock are generated with the second input clock having a phase that is programmably shifted relative to the first input clock when the system is operating at a lowered operating voltage or different temperature, for example. The first and second input clocks are coupled to a dually clocked flip flop, each having a primary latch and a secondary latch. A composite clock signal is generated in response to the first input clock and the second input clock. For example, a first signal is latched in the primary latch in response to the composite clock signal and a second signal is latched in the secondary latch in response to the first input clock signal.

Abstract: A computer system is provided for selecting an asset allocation for an investment portfolio intended to produce a target payout starting at a target date. The computer system is programmed to receive inputs that may relate to the target payout, the target date and a nominal rate of contributions to the investment portfolio. The computer system calculates a plurality of simulated investment outcomes based on assumed investment return rates and assumed inflation rates. The assumed investment return rates and assumed inflation rates are randomly selected in multi-year clusters from historical data. The computer system selects the asset allocation based on relative performance of the assumed asset allocations in the simulated investment outcomes.

Abstract: An exhaust diluting and diffusing apparatus includes a pipe mountable on a exhaust stack pipe, and having a flared skirt inlet to define an annular inlet, a mixing section adjacent the inlet, and an exhaust section formed as a pipe section with a multiplicity of holes. The apparatus pipe has a diameter greater than the diameter of the exhaust stack on which it is mounted.