Abstract: A method for integral semiconductor wafer map recording which comprises a semiconductor wafer (11) having a plurality of individual die (12, 13) thereon. Testing each of the individual die (12). Summarizing the results of the testing in a wafer map. Recording the wafer map on the semiconductor wafer (11) by laser scribing a binary code (19) within inactive die (13).

Abstract: A method of continuously self configuring a distributed control system. The method comprises scanning a plurality of potential address codes to locate an active object (13). Software senses an identity code (17) which is associated with the active object (13). Then a machine map (14) is built which provides the current address code (15, 31) of the active object (13). Within a network (28), a network map (21) is constructed by getting information from the appropriate machine map (14) for each computer (23). The network map (21) provides the current network address (32) of each active object (13) available to the network (28).

Abstract: A probe (10) that can be used for forming a low resistance electrical connection to a semiconductor die includes a contact (18) that is created on a compliant layer (12) which is supported by a substrate (11). Pressure applied to the contact (18) compresses the compliant layer (11) which causes a distal end of the contact (18) to move in a motion that is substantially equal to an arc. As the contact (18) moves through the arc motion, it scrubs across a bonding pad of a semiconductor die and breaks through oxide that typically forms on the bonding pad thereby forming a low resistance electrical connection to the bonding pad.

Abstract: An elastomeric element, having alternating layers of resistive and insulating material, is used to form isolation resistors. A surface of the elastomeric element is contacted with a conductor carrying electrical signals. Another surface is applied to the terminals of a semiconductor component thereby coupling the signals to the semiconductor component through the resistors formed by the elastomeric element.

Abstract: A method of testing unpackaged integrated circuits using a tester which is capable of testing a plurality of memories in parallel is provided. A membrane test head having a plurality of probe bumps thereon is provided wherein the probe bumps are coupled to the tester by microstrip transmission lines formed on the membrane test head. The semiconductor memory has a plurality of contact pads thereon which are coupled to the probes. In this manner, a plurality of semiconductor memories can be tested in wafer form. Alternatively, individual semiconductor memory chips can be mounted on a receiver plate and tested individually or in parallel by moving the receiver plate so that the contact pads couple to the probes.

Abstract: Apparatus and method of testing integrated circuits after the leads have been trimmed and partially formed, but before the package has been removed from the leadframe. One stage of a progressive trim and form process is adapted to test the integrated circuits by providing a membrane test head positioned underneath the IC package, wherein the membrane test head is coupled to an external tester. After the leads are electrically separated from each other end from the leadframe, the leads are aligned to the membrane test head and an inflatable bladder, which is positioned underneath the membrane test head, is inflated to couple the membrane test head to the leads. In this manner, one or more integrated circuits can be tested while still attached to the leadframe.

Abstract: An interface apparatus for coupling a multi-channel tester to a high pin count logic circuit for use in testing the logic circuit is provided wherein a plurality of terminal electronics units are coupled to each test channel of the multi-channel tester. Some of the terminal electronics units are coupled to each other in parallel by at least one stimulus shift register, which serves to divide a serial stimulus vector among the terminal electronics units, and one response shift register, which serve to assembly the response data from several terminal electronics units into a serial response vector. The serial stimulus vector is generated, and the serial response vector is analyzed by the multi-channel tester. The apparatus is capable of operating in one of a plurality of modes used for functional testing, parametric testing, and high speed scan path testing of the logic circuit.

Abstract: An assembly flow in which integrated circuits are burned-in and parametrically tested before assembly is provided. The integrated circuits are sorted based on the results of the parametric testing, and assembled in groups with similar parameters. Integrated circuits from a single group are assembled on a leadframe and encapsulated, marked, and tested again while still attached to the leadframe. Finally, the packaged integrated circuits are separated from the leadframe and those meeting predetermined parameters are loaded into carrier sleeves.

Abstract: An apparatus for use in high speed digital testing of high pin count logic circuits is provided wherein a plurality of terminal electronics units are connected in series to each other and to one channel of a multi-channel tester. Each pin electronics unit stores a test vector from the test channel in a first mode, and applies the test vector to the circuit under test at high speed in a second mode. Each pin electronics unit can also store response data from the circuit under test.

Abstract: A method of burning in integrated circuits on a semiconductor wafer is provided, wherein a burn-in chamber having a flexible membrane probe which is sized so that it can couple to a plurality of contact pads on the semiconductor wafer at one time. The semiconductor wafer is heated to a predetermined burn-in temperature and a bladder which lies behind the membrane probe is inflated so that the membrane probe couples to each of the plurality of contact pads on the wafer. The membrane probe is coupled to an exercise circuit which exercises all of the integrated circuits on the wafer in parallel for a predetermined time.