Patents by Inventor Hugh Wilkinson

Hugh Wilkinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180302341
    Abstract: Apparatus and methods for cableless connection of components within chassis and between separate chassis. Pairs of Extremely High Frequency (EHF) transceiver chips supporting very short length millimeter-wave wireless communication links are configured to pass radio frequency signals through holes in one or more metal layers in separate chassis and/or frames, enabling components in the separate chassis to communicate without requiring cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. The EHF-based wireless links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.
    Type: Application
    Filed: April 6, 2018
    Publication date: October 18, 2018
    Applicant: lntel Corporation
    Inventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Hugh Wilkinson, Amit Y. Kumar
  • Publication number: 20180212686
    Abstract: Apparatus and methods for rack level pre-installed interconnect for enabling cableless server, storage, and networking deployment. Plastic cable waveguides are configured to couple millimeter-wave radio frequency (RF) signals between two or more Extremely High Frequency (EHF) transceiver chips, thus supporting millimeter-wave wireless communication links enabling components in the separate chassis to communicate without requiring wire or optical cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. A plurality of plastic cable waveguide may be coupled to applicable support/mounting members, which in turn are mounted to a rack and/or top-of-rack switches. This enables the plastic cable waveguides to be pre-installed at the rack level, and further enables racks to be installed and replaced without requiring further cabling for the supported communication links.
    Type: Application
    Filed: January 18, 2018
    Publication date: July 26, 2018
    Applicant: lntel Corporation
    Inventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Hugh Wilkinson, Amit Y. Kumar
  • Patent number: 10033666
    Abstract: Examples include techniques for virtual Ethernet switching of a multi-node fabric. In some examples, first Ethernet links coupled with a group of Ethernet gateways are link aggregated. The group of Ethernet gateways couple with respective individual physical switch ports of a fabric switch of a multi-node fabric to form a default logical gateway to provide an uplink between a virtual Ethernet switch and an Ethernet network external to the multi-node fabric. Also, one or more individual Ethernet gateways coupled with respective individual physical switch ports of the fabric switch may be arranged to provide one or more respective downlinks between the virtual Ethernet switch and one or more Ethernet nodes external to the multi-node fabric via respective second Ethernet links coupled with the one or more individual Ethernet gateways.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Hugh Wilkinson, James C. Wright
  • Publication number: 20180191630
    Abstract: Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Applicant: INTEL CORPORATION
    Inventors: JONATHAN KENNY, NIALL D. MCDONNELL, ANDREW CUNNINGHAM, DEBRA BERNSTEIN, WILLIAM G. BURROUGHS, HUGH WILKINSON
  • Patent number: 9961018
    Abstract: Apparatus and methods for cableless connection of components within chassis and between separate chassis. Pairs of Extremely High Frequency (EHF) transceiver chips supporting very short length millimeter-wave wireless communication links are configured to pass radio frequency signals through holes in one or more metal layers in separate chassis and/or frames, enabling components in the separate chassis to communicate without requiring cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. The EHF-based wireless links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Hugh Wilkinson, Amit Y. Kumar
  • Publication number: 20180095892
    Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate source memory address information, and the instruction to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result is to include one of: (1) a page group identifier that is to correspond to a logical memory address that is to be based, at least in part, on the source memory address information; and (2) a set of page group metadata that is to correspond to the page group identifier. Other processors, methods, systems, and instructions are disclosed.
    Type: Application
    Filed: October 1, 2016
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Hugh Wilkinson, William R. Wheeler, Shirish Aundhe, Sandhya Viswanathan, David A. Koufaty
  • Publication number: 20180004655
    Abstract: A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Applicant: Intel Corporation
    Inventors: Hugh Wilkinson, William R. Wheeler, Debra Bernstein
  • Publication number: 20170373991
    Abstract: Examples include techniques for virtual Ethernet switching of a multi-node fabric. In some examples, first Ethernet links coupled with a group of Ethernet gateways are link aggregated. The group of Ethernet gateways couple with respective individual physical switch ports of a fabric switch of a multi-node fabric to form a default logical gateway to provide an uplink between a virtual Ethernet switch and an Ethernet network external to the multi-node fabric. Also, one or more individual Ethernet gateways coupled with respective individual physical switch ports of the fabric switch may be arranged to provide one or more respective downlinks between the virtual Ethernet switch and one or more Ethernet nodes external to the multi-node fabric via respective second Ethernet links coupled with the one or more individual Ethernet gateways.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventors: HUGH WILKINSON, JAMES C. WRIGHT
  • Publication number: 20170286337
    Abstract: Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Ren Wang, Yipeng Wang, Jr-Shian Tsai, Andrew Herdrich, Tsung-Yuan Tai, Niall McDonnell, Stephen Van Doren, David Sonnier, Debra Bernstein, Hugh Wilkinson, Narender Vangati, Stephen Miller, Gage Eads, Andrew Cunningham, Jonathan Kenny, Bruce Richardson, William Burroughs, Joseph Hasting, An Yan, James Clee, Te Ma, Jerry Pirog, Jamison Whitesell
  • Publication number: 20170272370
    Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Applicant: Intel Corporation
    Inventors: ILANGO GANGA, ALAIN GRAVEL, THOMAS D. LOVETT, RADIA PERLMAN, GREG REGNIER, ANIL VASUDEVAN, HUGH WILKINSON
  • Publication number: 20170192921
    Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.
    Type: Application
    Filed: January 4, 2016
    Publication date: July 6, 2017
    Inventors: Ren Wang, Yipeng Wang, Andrew J. Herdrich, Jr-Shian Tsai, Tsung-Yuan C. Tai, Niall D. McDonnell, Hugh Wilkinson, Bradley A. Burres, Bruce Richardson, Namakkal N. Venkatesan, Debra Bernstein, Edwin Verplanke, Stephen R. Van Doren, An Yan, Andrew Cunningham, David Sonnier, Gage Eads, James T. Clee, Jamison D. Whitesell, Jerry Pirog, Jonathan Kenny, Joseph R. Hasting, Narender Vangati, Stephen Miller, Te K. Ma, William Burroughs
  • Publication number: 20170180271
    Abstract: Techniques for embedding fabric addressing information within Ethernet media access control (MAC) addresses is disclosed herein and allows a multi-node fabric having potentially millions of nodes to feature Ethernet encapsulation without the necessity of a lookup or map to translate MAC addresses to fabric-routable local identifiers (LIDs). In particular, a locally-administered MAC address may be encoded with fabric addressing information including a LID. Thus a node may exchange Ethernet packets using a multi-node fabric by encapsulating each Ethernet packet with a destination MAC address corresponding to an intended destination. As the destination MAC address may implicitly map to a LID of the multi-node fabric, the node may use an extracted LID value therefrom to address a fabric-routable packet. To this end, a node may introduce a fabric-routable packet encapsulating an Ethernet packet onto a multi-node fabric without necessarily performing a lookup to map a MAC address to a corresponding LID.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: Intel Corporation
    Inventors: HUGH WILKINSON, JAMES C. WRIGHT
  • Patent number: 9674098
    Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: June 6, 2017
    Assignee: INTEL CORPORATION
    Inventors: Ilango Ganga, Alain Gravel, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson, Thomas D. Lovett
  • Publication number: 20170126330
    Abstract: Apparatus and methods for rack level pre-installed interconnect for enabling cableless server, storage, and networking deployment. Plastic cable waveguides are configured to couple millimeter-wave radio frequency (RF) signals between two or more Extremely High Frequency (EHF) transceiver chips, thus supporting millimeter-wave wireless communication links enabling components in the separate chassis to communicate without requiring wire or optical cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. A plurality of plastic cable waveguide may be coupled to applicable support/mounting members, which in turn are mounted to a rack and/or top-of-rack switches. This enables the plastic cable waveguides to be pre-installed at the rack level, and further enables racks to be installed and replaced without requiring further cabling for the supported communication links.
    Type: Application
    Filed: October 21, 2016
    Publication date: May 4, 2017
    Applicant: lntel Corporation
    Inventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Hugh Wilkinson, Amit Y. Kumar
  • Publication number: 20160380923
    Abstract: Apparatus and methods for cableless connection of components within chassis and between separate chassis. Pairs of Extremely High Frequency (EHF) transceiver chips supporting very short length millimeter-wave wireless communication links are configured to pass radio frequency signals through holes in one or more metal layers in separate chassis and/or frames, enabling components in the separate chassis to communicate without requiring cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. The EHF-based wireless links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.
    Type: Application
    Filed: September 12, 2016
    Publication date: December 29, 2016
    Applicant: lntel Corporation
    Inventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Hugh Wilkinson, Amit Y. Kumar
  • Patent number: 9496592
    Abstract: Apparatus and methods for rack level pre-installed interconnect for enabling cableless server, storage, and networking deployment. Plastic cable waveguides are configured to couple millimeter-wave radio frequency (RF) signals between two or more Extremely High Frequency (EHF) transceiver chips, thus supporting millimeter-wave wireless communication links enabling components in the separate chassis to communicate without requiring wire or optical cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. A plurality of plastic cable waveguide may be coupled to applicable support/mounting members, which in turn are mounted to a rack and/or top-of-rack switches. This enables the plastic cable waveguides to be pre-installed at the rack level, and further enables racks to be installed and replaced without requiring further cabling for the supported communication links.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Hugh Wilkinson, Amit Y. Kumar
  • Patent number: 9450635
    Abstract: Apparatus and methods for cableless connection of components within chassis and between separate chassis. Pairs of Extremely High Frequency (EHF) transceiver chips supporting very short length millimeter-wave wireless communication links are configured to pass radio frequency signals through holes in one or more metal layers in separate chassis and/or frames, enabling components in the separate chassis to communicate without requiring cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. The EHF-based wireless links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: September 20, 2016
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Hugh Wilkinson, Amit Y. Kumar
  • Publication number: 20150288410
    Abstract: Apparatus and methods for cableless connection of components within chassis and between separate chassis. Pairs of Extremely High Frequency (EHF) transceiver chips supporting very short length millimeter-wave wireless communication links are configured to pass radio frequency signals through holes in one or more metal layers in separate chassis and/or frames, enabling components in the separate chassis to communicate without requiring cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. The EHF-based wireless links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 8, 2015
    Inventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Hugh Wilkinson, Amit Y. Kumar
  • Publication number: 20150280827
    Abstract: Apparatus and methods for rack level pre-installed interconnect for enabling cableless server, storage, and networking deployment. Plastic cable waveguides are configured to couple millimeter-wave radio frequency (RF) signals between two or more Extremely High Frequency (EHF) transceiver chips, thus supporting millimeter-wave wireless communication links enabling components in the separate chassis to communicate without requiring wire or optical cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. A plurality of plastic cable waveguide may be coupled to applicable support/mounting members, which in turn are mounted to a rack and/or top-of-rack switches. This enables the plastic cable waveguides to be pre-installed at the rack level, and further enables racks to be installed and replaced without requiring further cabling for the supported communication links.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Hugh Wilkinson, Amit Y. Kumar
  • Publication number: 20150117177
    Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.
    Type: Application
    Filed: September 25, 2014
    Publication date: April 30, 2015
    Inventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson