Abstract: The present invention relates to an electronic watch allowing data to be received, comprising: An electrical energy source A control member arranged to be supplied with power by the electrical energy source A receiver module comprising: An optical sensor capable of detecting a sequence of light pulses modulated by data, and of converting said sequence into a digital signal An energy storage element arranged to store electrical energy generated by the optical sensor A demodulator arranged to be supplied with power by the energy storage element, capable of extracting the data from the digital signal Transmission means capable of transmitting the extracted data to the control member.

Abstract: The integrated circuit connection device (1) enables an external component to be connected. The integrated circuit is powered by a supply voltage (VDD) and part of the circuit operates using at least one internal regulated voltage (VREG). The connection device includes two active transistors (N1, P1) of different conductivity connected in series between the supply voltage (VDD) and earth (VSS). The drains of these two active transistors (N1, P1) are connected to each other so as to form an external contact pad (2). The gates of these active transistors are controlled by voltage signals that have the same amplitude (Vesd). The connection device further includes switching means (3) for modifying the control signals (Vesd) applied across the active transistor gates, without exceeding the highest voltage between the supply voltage (VDD) and the internal regulated voltage (VREG).

Abstract: The present invention relates to an electronic watch allowing data to be received, comprising: An electrical energy source A control member arranged to be supplied with power by the electrical energy source A receiver module comprising: An optical sensor capable of detecting a sequence of light pulses modulated by data, and of converting said sequence into a digital signal An energy storage element arranged to store electrical energy generated by the optical sensor A demodulator arranged to be supplied with power by the energy storage element, capable of extracting the data from the digital signal Transmission means capable of transmitting the extracted data to the control member

Abstract: The processor circuit (1) has a Harvard architecture. This processor circuit includes a calculation unit (2), a first memory element (3a) for data storage and a second memory element (4a) for instruction storage. Said first and second memory elements (3a, 4a) are connected by at least one communication bus (5, 6) to the calculation unit. The processor circuit includes management means (8), placed between the first and second memory elements and the calculation unit and capable of saving several data items or instructions to save time during successive data reading.

Abstract: The processor circuit (1) has a Harvard architecture. This processor circuit includes a calculation unit (2), a first memory element (3a) for data storage and a second memory element (4a) for instruction storage. Said first and second memory elements (3a, 4a) are connected by at least one communication bus (5, 6) to the calculation unit. The processor circuit includes management means (8), placed between the first and second memory elements and the calculation unit and capable of saving several data items or instructions to save time during successive data reading.

Abstract: The integrated circuit connection device (1) enables an external component to be connected. The integrated circuit is powered by a supply voltage (VDD) and part of the circuit operates using at least one internal regulated voltage (VREG). The connection device includes two active transistors (N1, P1) of different conductivity connected in series between the supply voltage (VDD) and earth (VSS). The drains of these two active transistors (N1, P1) are connected to each other so as to form an external contact pad (2). The gates of these active transistors are controlled by voltage signals that have the same amplitude (Vesd). The connection device further includes switching means (3) for modifying the control signals (Vesd) applied across the active transistor gates, without exceeding the highest voltage between the supply voltage (VDD) and the internal regulated voltage (VREG).

Abstract: The reading device enables a non-volatile memory consisting of a matrix of memory cells (TM) to be read. Once the memory cells have been selected to be read in a read cycle controlled by a microprocessor unit, sense amplifiers (4) activated at the start of each cycle supply a binary data word (dx) representing the reading of the selected memory cells. The reading device also comprises time-lag means (3, MF, TF, Cgap) activated at the start of each read cycle. These time-lag means supply a reference signal (rd_mon) that controls the read time of the cells selected independently of the microprocessor unit. This read time is determined so that it is sufficient for reading all the valid data of the selected memory cells in each read cycle.

Abstract: The integrated circuit device (1) backs up the configuration of output terminals (O, SP) of said integrated circuit in low-power mode. To do this, the device includes several voltage level shift units (2, 2?, 2?, 2??) and an output stage (3) connected to each output of the level shift units and connected to at least one external contact pad (SP) of said integrated circuit. Each level shift unit includes an input stage powered by a regulated internal voltage (VREG) and a part for transferring the state of a specific output function, which is powered by a supply voltage (VDD) of the integrated circuit. Each level shift unit also includes a memory cell at output powered by the supply voltage, for storing the output state of a specific function of the level shift unit in the idle mode of the integrated circuit where the regulated voltage is cut off.

Abstract: The integrated circuit device (1) backs up the configuration of output terminals (O, SP) of said integrated circuit in low-power mode. To do this, the device includes several voltage level shift units (2, 2?, 2?, 2??) and an output stage (3) connected to each output of the level shift units and connected to at least one external contact pad (SP) of said integrated circuit. Each level shift unit includes an input stage powered by a regulated internal voltage (VREG) and a part for transferring the state of a specific output function, which is powered by a supply voltage (VDD) of the integrated circuit. Each level shift unit also includes a memory cell at output powered by the supply voltage, for storing the output state of a specific function of the level shift unit in the idle mode of the integrated circuit where the regulated voltage is cut off.

Abstract: The reading device enables a non-volatile memory consisting of a matrix of memory cells (TM) to be read. Once the memory cells have been selected to be read in a read cycle controlled by a microprocessor unit, sense amplifiers (4) activated at the start of each cycle supply a binary data word (dx) representing the reading of the selected memory cells. The reading device also comprises time-lag means (3, MF, TF, Cgap) activated at the start of each read cycle. These time-lag means supply a reference signal (rd_mon) that controls the read time of the cells selected independently of the microprocessor unit. This read time is determined so that it is sufficient for reading all the valid data of the selected memory cells in each read cycle. The time-lag means mainly comprise a reference dummy cell (TF) linked to a reference sense amplifier (3), which supplies the reference signal (rd_mon), and a time-lag capacitor (Cgap) linked to the dummy cell.

Abstract: The present invention concerns a control device (21) for a liquid crystal display cell (1) including electrodes (1.1a; 1.1b; 1.1c) forming segments and/or symbols. This device includes control means (33a; 33b; 33c) for providing control signals to said electrodes; and a matrix network of connection paths (45; 47; 49; 50) whose columns (49; 50) are connected to said control means, and whose lines (45; 47) are connected to receive address signals and data signals representative of said control signals. This device further includes switching means (52) arranged at each of the intersections of said network, each of said switching means being arranged so as to be able to be switched permanently into the conducting state or the non conducting state, in accordance with a circuit layout predetermined as a function of said cell.