Abstract: This invention relates to a system level power evaluation method in which detailed power macro-models (PMM) are created for operations of modules. These PMMs are stored in memory. A system level circuit description (SLCD) is evaluated using the PMMs stored in memory that are relevant to that SLCD and using other PMMs that are generated for operations of modules that do not have PMMs stored in memory. In this way, a highly accurate and computationally efficient power evaluation of the SLCD is possible. Furthermore, the user implementing the method may define a case, which relates to an operation of a module and has a PMM associated therewith, in a highly flexible manner that allows for more abstract analysis of the SLCD to be carried out. A case may relate to a single operation of a module, a plurality of operations of a module or operation(s) of a plurality of modules.

Abstract: This invention relates to a method and processor (19) for power analysis in digital circuits. The method incorporates a main processor (19) and an associative memory mechanism (101a, 101b, 102, 104, 105, 106), the associative memory mechanism comprising a plurality of associative arrays (101a, 101b), an input value register (102), at least one result register (104) and a memory block area (29). A circuit design is transformed into a functionally equivalent model format suitable for processing in the associative array and thereafter input vectors are applied to the circuit and a record is kept of the inputs and or the outputs on each of the gates in the circuit over a specified time period. In this way, it is possible to calculate the leakage power dissipation as well as both the toggle dynamic power and the transition dynamic power.