Patents by Inventor Hugo Saleh
Hugo Saleh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916602Abstract: A remote memory system includes a substrate of a multi-chip package, an integrated circuit chip connected to the substrate, and an electro-optical chip connected to the substrate. The integrated circuit chip includes a high-bandwidth memory interface. An electrical interface of the electro-optical chip is electrically connected to the high-bandwidth memory interface. A photonic interface of the electro-optical chip is configured to optically connect with an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals received through the electrical interface from the high-bandwidth interface into outgoing optical data signals. The optical macro transmits the outgoing optical data signals through the photonic interface to the optical link. The optical macro also converts incoming optical data signals received through the photonic interface into incoming electrical data signals.Type: GrantFiled: February 14, 2021Date of Patent: February 27, 2024Assignee: Ayar Labs, Inc.Inventors: Roy Edward Meade, Vladimir Stojanovic, Chen Sun, Mark Wade, Hugo Saleh, Charles Wuischpard
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Publication number: 20230370170Abstract: A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.Type: ApplicationFiled: July 18, 2023Publication date: November 16, 2023Inventors: Roy Edward Meade, Vladimir Stojanovic, Chen Sun, Mark Wade, Hugo Saleh, Charles Wuischpard
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Patent number: 11705972Abstract: A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.Type: GrantFiled: January 25, 2022Date of Patent: July 18, 2023Assignee: Ayar Labs, Inc.Inventors: Roy Edward Meade, Vladimir Stojanovic, Chen Sun, Mark Wade, Hugo Saleh, Charles Wuischpard
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Publication number: 20220166533Abstract: A network switch system-in-package includes a carrier substrate with a network switch chip and a plurality of photonic input/output modules disposed on the carrier substrate. Each of the plurality of photonic input/output modules includes a module substrate and a plurality of photonic chip pods disposed on the module substrate. Each photonic chip pod includes a pod substrate with a photonic input/output chiplet and a gearbox chiplet attached to the pod substrate. The photonic input/output chiplet includes a parallel electrical interface, a photonic interface, and a plurality of optical macros implemented between the photonic interface and the parallel electrical interface. The gearbox chiplet electrically connects with the parallel electrical interface of the photonic input/output chiplet and a serial electrical interface of the network switch chip.Type: ApplicationFiled: November 16, 2021Publication date: May 26, 2022Inventors: Vladimir Stojanovic, Hugo Saleh, Roy Edward Meade
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Publication number: 20220148627Abstract: A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.Type: ApplicationFiled: January 25, 2022Publication date: May 12, 2022Inventors: Roy Edward Meade, Vladimir Stojanovic, Chen Sun, Mark Wade, Hugo Saleh, Charles Wuischpard
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Patent number: 11233580Abstract: A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.Type: GrantFiled: February 14, 2021Date of Patent: January 25, 2022Assignee: Ayar Labs, Inc.Inventors: Roy Edward Meade, Vladimir Stojanovic, Chen Sun, Mark Wade, Hugo Saleh, Charles Wuischpard
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Publication number: 20210258078Abstract: A remote memory system includes a substrate of a multi-chip package, an integrated circuit chip connected to the substrate, and an electro-optical chip connected to the substrate. The integrated circuit chip includes a high-bandwidth memory interface. An electrical interface of the electro-optical chip is electrically connected to the high-bandwidth memory interface. A photonic interface of the electro-optical chip is configured to optically connect with an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals received through the electrical interface from the high-bandwidth interface into outgoing optical data signals. The optical macro transmits the outgoing optical data signals through the photonic interface to the optical link. The optical macro also converts incoming optical data signals received through the photonic interface into incoming electrical data signals.Type: ApplicationFiled: February 14, 2021Publication date: August 19, 2021Inventors: Roy Edward Meade, Vladimir Stojanovic, Chen Sun, Mark Wade, Hugo Saleh, Charles Wuischpard
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Publication number: 20210257021Abstract: A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.Type: ApplicationFiled: February 14, 2021Publication date: August 19, 2021Inventors: Roy Edward Meade, Vladimir Stojanovic, Chen Sun, Mark Wade, Hugo Saleh, Charles Wuischpard
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Patent number: 7272061Abstract: Dynamic control of a pre-charge level particularly for memory cells is described. In one example, a circuit block has pre-charge node and a power supply is coupled to the pre-charge node to provide either a first power level or a second power level when the circuit block is not active. The first power level may be a pre-charge mode power level and the second power level may be a sleep mode power level.Type: GrantFiled: January 24, 2005Date of Patent: September 18, 2007Assignee: Intel CorporationInventor: Hugo Saleh
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Publication number: 20060164904Abstract: Dynamic control of a pre-charge level particularly for memory cells is described. In one example, a circuit block has pre-charge node and a power supply is coupled to the pre-charge node to provide either a first power level or a second power level when the circuit block is not active. The first power level may be a pre-charge mode power level and the second power level may be a sleep mode power level.Type: ApplicationFiled: January 24, 2005Publication date: July 27, 2006Inventor: Hugo Saleh