Patents by Inventor Hugo Van Hove

Hugo Van Hove has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Layout configurable electrostatic discharge device for integrated circuits
    Patent number: 6707110
    Abstract: Electrostatic discharge protection device comprising a first highly p-doped region with a base contact, a first highly n-doped region with a collector contact, a second highly n-doped region with an emitter contact and located between the first highly p-doped region and the second highly n-doped region, the first highly p-doped region and the second highly n-doped region being applied in a weakly p-doped region which a has a lateral overlap extending towards the first highly n-doped region, the lateral overlap having a width, the first highly n-doped region being applied in a weakly n-doped region, the weakly p-doped region and the weakly n-doped region being applied in a more weakly n-doped region, and a highly n-doped buried layer located underneath the more weakly n-doped region and extending below at least a portion of the weakly n-doped region and at least a portion of the weakly p-doped region.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: March 16, 2004
    Assignees: Interuniversitair Microelektronica Centrum, Alcatel SA
    Inventors: Vincent De Heyn, Guido Groeseneken, Louis Vacaresse, Geert Gallopyn, Hugo Van Hove
  • Layout configurable electrostatic discharge device for integrated circuits
    Publication number: 20030006464
    Abstract: Electrostatic discharge protection device comprising a first highly p-doped region with a base contact, a first highly n-doped region with a collector contact, a second highly n-doped region with an emitter contact and located between the first highly p-doped region and the second highly n-doped region, the first highly p-doped region and the second highly n-doped region being applied in a weakly p-doped region which a has a lateral overlap extending towards the first highly n-doped region, the lateral overlap having a width, the first highly n-doped region being applied in a weakly n-doped region, the weakly p-doped region and the weakly n-doped region being applied in a more weakly n-doped region, and a highly n-doped buried layer located underneath the more weakly n-doped region and extending below at least a portion of the weakly n-doped region and at least a portion of the weakly p-doped region.
    Type: Application
    Filed: April 25, 2002
    Publication date: January 9, 2003
    Inventors: Vincent De Heyn, Guido Groeseneken, Louis Vacaresse, Geert Gallopyn, Hugo Van Hove
  • Method of processing a high voltage p++/n-well junction and a device manufactured by the method
    Publication number: 20020070411
    Abstract: The present invention is related to a method of processing a high voltage p++/n-well junction on a substrate comprising at least one n-well region and at least one p-well region. The method comprises performing a p-type implantation in a zone surrounding said high voltage p++/n-well junction independently from other implantation.
    Type: Application
    Filed: September 10, 2001
    Publication date: June 13, 2002
    Applicant: Alcatel
    Inventors: Miguel Vermandel, Andre Van Calster, Peter Moens, Hugo Van Hove, Marnix Tack