Abstract: A technique for decoding an encoded bitstream of digital video content involves decoding a bitstream, wherein decoding the bitstream generates decoded syntax elements and decoded pixel information, creating an access point in the currently decoded bitstream by saving state information related to the decoding, saving the decoded syntax elements, and saving the decoded pixel information, and synchronizing a subsequent decoding operation to the access point utilizing the saved state information, the saved decoded syntax elements, and the saved decoded pixel information.

Abstract: A data processing system comprises a memory, a memory protection unit, and one or more IP units connected to the memory via the memory protection unit. The memory protection unit is arranged to logically partition the memory into different regions, to maintain a policy for each region, the policy defining access rights to the respective region and defining the safety status of data written in the respective region, to check access requests writing data from a first region to a second region, and to refuse the access request if the safety status, according to the respective policy, of the written data in the second region is not maintained.

Abstract: A technique for decoding an encoded bitstream of digital video content involves decoding a bitstream, wherein decoding the bitstream generates decoded syntax elements and decoded pixel information, creating an access point in the currently decoded bitstream by saving state information related to the decoding, saving the decoded syntax elements, and saving the decoded pixel information, and synchronizing a subsequent decoding operation to the access point utilizing the saved state information, the saved decoded syntax elements, and the saved decoded pixel information.

Abstract: The present invention provides for a dual interface memory arrangement employing the checkered memory mapping formed from combined vertically and horizontally sliced memory mapping, and including 2D access means arranged for access to the mapping memory wherein the said to the access means is arranged such that the access overlaps memory mapped to both interfaces both horizontally and vertically, and which arrangement preferably provides for two DTL channels for each interface wherein a highly efficient unified memory arrangement can be achieved for all processing aspects such as CPU, audio, video and gfx processing.