Patents by Inventor Hugues Labbe

Hugues Labbe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10893299
    Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Jill Boyce, Scott Janus, Itay Kaufman, Archie Sharma, Stanley Baran, Michael Apodaca, Prasoonkumar Surti, Srikanth Potluri, Barnan Das, Hugues Labbe, Jong Dae Oh, Gokcen Cilingir, Maria Bortman, Tzach Ashkenazi, Jonathan Distler, Atul Divekar, Mayuresh M. Varerkar, Narayan Biswal, Nilesh V. Shah, Atsuo Kuwahara, Kai Xiao, Jason Tanner, Jeffrey Tripp
  • Patent number: 10878614
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer KP, Jonathan Kennedy, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Tomer Bar-On, Carsten Benthin, Adam T. Lake, Vasanth Ranganathan, Abhishek R. Appu
  • Publication number: 20200402270
    Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
    Type: Application
    Filed: July 2, 2020
    Publication date: December 24, 2020
    Inventors: Karthik Vaidyanathan, Prasoonkumar Surti, Hugues Labbe, Atsuo Kuwahara, Sameer KP, Jonathan Kennedy, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh
  • Patent number: 10867583
    Abstract: Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Hugues Labbe, Karthik Vaidyanathan, Prasoonkumar Surti, Atsuo Kuwahara, Sameer Kp, Jonathan Kennedy
  • Patent number: 10846918
    Abstract: Systems, apparatuses, and methods may provide for technology to render and compress stereoscopic graphical data. In one example, the technology identifies, from graphical data associated with a stereoscopic image defined by a first perspective view and a second perspective view, a background region and a foreground region of a graphical scene in the stereoscopic image, renders graphical data of the identified background region for the first perspective view, and compresses the rendered graphical data.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: John G. Gierach, Hugues Labbe, Tomer Bar-On, Adam T. Lake, Kai Xiao, Ankur N. Shah, Philip R. Laws, Devan Burke, Abhishek R. Appu, Peter L. Doyle, Elmoustapha Ould-Ahmed-Vall, Travis T. Schluessler, Altug Koker
  • Publication number: 20200357092
    Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Hugues Labbe, Tomer Bar-On, Kai Xiao, Ankur N. Shah, John G. Gierach
  • Publication number: 20200334896
    Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.
    Type: Application
    Filed: May 4, 2020
    Publication date: October 22, 2020
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer Kp, Jonathan Kennedy, Abhishek R. Appu, Jeffery S. Boles, Balaji Vembu, Michael Apodaca, Slawomir Grajewski, Gabor Liktor, David M. Cimini, Andrew T. Lauritzen, Travis T. Schluessler, Murali Ramadoss, Abhishek Venkatesh, Joydeep Ray, Kai Xiao, Ankur N. Shah, Altug Koker
  • Publication number: 20200334200
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: May 7, 2020
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Guei-Yuan Lueh, Abhishek R. Appu, Joydeep Ray, Balaji Vembu, Tomer Bar-On, Andrew T. Lauritzen, Hugues Labbe, John G. Gierach, Gabor Liktor
  • Patent number: 10719917
    Abstract: Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Tomer Bar-On, Hugues Labbe, Adam T. Lake, Kai Xiao, Ankur N. Shah, Johannes Guenther, Abhishek R. Appu, Joydeep Ray, Deepak S. Vembar, ElMoustapha Ould-Ahmed-Vall
  • Patent number: 10706591
    Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Karthik Vaidyanathan, Prasoonkumar Surti, Hugues Labbe, Atsuo Kuwahara, Sameer Kp, Jonathan Kennedy, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh
  • Publication number: 20200160534
    Abstract: Systems, apparatuses and methods may provide for technology that partitions a three-dimensional (3D) scene into a plurality of layers including at least a foreground layer and a background layer. Additionally, the foreground layer may be rendered at a first rate and the background layer may be rendered at a second frame rate, wherein the first frame rate is greater than the second frame rate. In one example, the foreground layer and the background layer are composited into a frame.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Hugues Labbe, Tomer Bar-On, John G. Gierach, Gabor Liktor, Andrew T. Lauritzen
  • Patent number: 10649956
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: May 12, 2020
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Guei-Yuan Lueh, Abhishek R. Appu, Joydeep Ray, Balaji Vembu, Tomer Bar-On, Andrew T. Lauritzen, Hugues Labbe, John G. Gierach, Gabor Liktor
  • Patent number: 10643374
    Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer Kp, Jonathan Kennedy, Abhishek R. Appu, Jeffery S. Boles, Balaji Vembu, Michael Apodaca, Slawomir Grajewski, Gabor Liktor, David M. Cimini, Andrew T. Lauritzen, Travis T. Schluessler, Murali Ramadoss, Abhishek Venkatesh, Joydeep Ray, Kai Xiao, Ankur N. Shah, Altug Koker
  • Publication number: 20200118526
    Abstract: Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 16, 2020
    Inventors: Hugues Labbe, Karthik Vaidyanathan, Prasoonkumar Surti, Atsuo Kuwahara, Sameer Kp, Jonathan Kennedy
  • Publication number: 20200097243
    Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 27, 2019
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Deepak S. Vembar, Atsuo Kuwahara, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hugues Labbe, Altug Koker, Michael Apodaca, Kai Xiao, Jeffery S. Boles, Adam T. Lake, David M. Cimini, Balaji Vembu, Elmoustapha Ould-Ahmed-Vall, Jacek Kwiatkowski, Philip R. Laws, Ankur N. Shah, Abhishek R. Appu, Joydeep Ray, Wenyin Fu, Nikos Kaburlasos, Prasoonkumar Surti, Bhushan M. Borole
  • Publication number: 20200073810
    Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.
    Type: Application
    Filed: September 10, 2019
    Publication date: March 5, 2020
    Inventors: Andrew T. Lauritzen, Gabor Liktor, Tomer Bar-On, Hugues Labbe, John G. Gierach, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, Balaji Vembu, Altug Koker
  • Publication number: 20200051309
    Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.
    Type: Application
    Filed: August 9, 2019
    Publication date: February 13, 2020
    Applicant: Intel Corporation
    Inventors: HUGUES LABBE, DARREL PALKE, SHERINE ABDELHAK, JILL BOYCE, VARGHESE GEORGE, SCOTT JANUS, ADAM LAKE, ZHIJUN LEI, ZHENGMIN LI, MIKE MACPHERSON, CARL MARSHALL, SELVAKUMAR PANNEER, PRASOONKUMAR SURTI, KARTHIK VEERAMANI, DEEPAK VEMBAR, VALLABHAJOSYULA SRINIVASA SOMAYAZULU
  • Publication number: 20200045343
    Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Applicant: Intel Corporation
    Inventors: Jill Boyce, Scott Janus, Itay Kaufman, Archie Sharma, Stanley Baran, Michael Apodaca, Prasoonkumar Surti, Srikanth Potluri, Barnan Das, Hugues Labbe, Jong Dae Oh, Gokcen Cilingir, Maria Bortman, Tzach Ashkenazi, Jonathan Distler, Atul Divekar, Mayuresh M. Varerkar, Narayan Biswal, Nilesh V. Shah, Atsuo Kuwahara, Kai Xiao, Jason Tanner, Jeffrey Tripp
  • Publication number: 20200043182
    Abstract: Embodiments described herein provide an apparatus comprising a processor to divide a first point cloud data set frame representing a three dimensional space at a first point in time into a matrix of blocks, determine at least one three dimensional (3D) motion vector for at least a subset of blocks in the matrix of blocks, generate a predicted second point cloud data set frame representing a prediction of the three dimensional space at a second point in time by applying the at least one 3D motion vector to the subset of blocks in the matrix of blocks, compare the predicted second point cloud data set frame to a second point cloud data set frame representing a prediction of the three dimensional space at a second point in time to generate a prediction error parameter, and encode the second point cloud data set frame as a function of the first point cloud data set frame and the at least one three dimensional (3D) motion vector when the prediction error factor is beneath an error threshold to produce an encoded s
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Applicant: Intel Corporation
    Inventors: Scott Janus, Barnan Das, Hugues Labbe, Jong Dae Oh, Gokcen Cilingir, James Holland, Narayan Biswal, Yi-Jen Chiu, Qian Xu, Mayuresh Varerkar, Sang-Hee Lee, Stanley Baran, Srikanth Potluri, Jason Ross, Maruthi Sandeep Maddipatla
  • Publication number: 20200045348
    Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to decode point cloud data, reconstruct the decoded point cloud data and fill one or more holes in reconstructed point cloud frame data using patch metadata included in the decoded point cloud data and a memory communicatively coupled to the one or more processors.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Applicant: Intel Corporation
    Inventors: Jill Boyce, Scott Janus, Prasoonkumar Surti, Stanley Baran, Michael Apodaca, Srikanth Potluri, Hugues Labbe, Jong Dae Oh, Gokcen Cilingir, Archie Sharma, Jeffrey Tripp, Jason Ross, Barnan Das