Patents by Inventor Hugues Marchand

Hugues Marchand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11133408
    Abstract: A passivated semiconductor device structure includes a III-nitride structure and a passivation layer. The III-nitride structure includes a high electron mobility transistor (HEMT). The passivation layer includes a dielectric, which is formed over the structure to provide passivation and forms an interface with the structure. The interface provides a transition between the structure and the dielectric having a thickness of at least two atomic layers. The interface also has a characteristic density of interface states less than a reference density of interface states that corresponds to a thickness of at most one atomic layer. The transition, which constitutes a rough interface, allows a relatively low density of interface states, and thus improves high-frequency performance of the device structure.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: September 28, 2021
    Assignee: IQE plc
    Inventors: Oleg Laboutin, Xiang Gao, Hugues Marchand
  • Publication number: 20210043760
    Abstract: A passivated semiconductor device structure includes a III-nitride structure and a passivation layer. The III-nitride structure includes a high electron mobility transistor (HEMT). The passivation layer includes a dielectric, which is formed over the structure to provide passivation and forms an interface with the structure. The interface provides a transition between the structure and the dielectric having a thickness of at least two atomic layers. The interface also has a characteristic density of interface states less than a reference density of interface states that corresponds to a thickness of at most one atomic layer. The transition, which constitutes a rough interface, allows a relatively low density of interface states, and thus improves high-frequency performance of the device structure.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 11, 2021
    Inventors: Oleg Laboutin, Xiang Gao, Hugues Marchand
  • Patent number: 10580871
    Abstract: Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 3, 2020
    Assignee: IQE plc
    Inventors: Oleg Laboutin, Chen-Kai Kao, Chien-Fong Lo, Wayne Johnson, Hugues Marchand
  • Patent number: 10347794
    Abstract: Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. The method can further include forming a volume of gallium nitride carried by the crystals, with the selected orientation of the crystals at least partially controlling a crystal orientation of the gallium nitride, and without bonding the gallium nitride, as a unit, to the support member. In other embodiments, the number of crystals can be increased by a process that includes annealing a region in which the crystals are present, etching the region to remove crystals having an orientation other than the selected orientation, and/or growing the crystals having the selected orientation.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: July 9, 2019
    Assignee: Qromis, Inc.
    Inventors: Anthony Lochtefeld, Hugues Marchand
  • Publication number: 20180277639
    Abstract: Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 27, 2018
    Inventors: Oleg Laboutin, Chen-Kai Kao, Chien-Fong Lo, Wayne Johnson, Hugues Marchand
  • Patent number: 9917156
    Abstract: Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: March 13, 2018
    Assignee: IQE, plc
    Inventors: Oleg Laboutin, Chen-Kai Kao, Chien-Fong Lo, Wayne Johnson, Hugues Marchand
  • Publication number: 20180069085
    Abstract: Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
    Type: Application
    Filed: September 2, 2016
    Publication date: March 8, 2018
    Inventors: Oleg Laboutin, Chen-Kai Kao, Chien-Fong Lo, Wayne Johnson, Hugues Marchand
  • Patent number: 9691712
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 27, 2017
    Assignee: The Regents of the University of California
    Inventors: Hugues Marchand, Brendan J. Moran, Umesh K. Mishra, James S. Speck
  • Publication number: 20170170283
    Abstract: A III-nitride structure can include a silicon substrate, a nucleation layer over the silicon substrate, and a carbon-doped buffer layer over the nucleation layer. The carbon-doped buffer layer can include a III-nitride material and a concentration of carbon that is greater than 1×1020 cm?3. The III-nitride structure can include a III-nitride channel layer over the carbon-doped buffer layer and a III-nitride barrier layer over the III-nitride channel layer. The carbon doping to a carbon concentration greater than 1×1020 cm?3 can increase the compressive stress in the III-nitride structure.
    Type: Application
    Filed: December 5, 2016
    Publication date: June 15, 2017
    Inventors: Oleg Laboutin, Chen-Kai Kao, Chien-Fong Lo, Hugues Marchand, Rodney Pelzel
  • Patent number: 9129977
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: September 8, 2015
    Assignee: The Regents of the University of California
    Inventors: Hugues Marchand, Brendan J. Moran, Umesh K. Mishra, James S. Speck
  • Publication number: 20150221832
    Abstract: Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. The method can further include forming a volume of gallium nitride carried by the crystals, with the selected orientation of the crystals at least partially controlling a crystal orientation of the gallium nitride, and without bonding the gallium nitride, as a unit, to the support member. In other embodiments, the number of crystals can be increased by a process that includes annealing a region in which the crystals are present, etching the region to remove crystals having an orientation other than the selected orientation, and/or growing the crystals having the selected orientation.
    Type: Application
    Filed: April 17, 2015
    Publication date: August 6, 2015
    Inventors: Anthony Lochtefeld, Hugues Marchand
  • Patent number: 9012253
    Abstract: Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. The method can further include forming a volume of gallium nitride carried by the crystals, with the selected orientation of the crystals at least partially controlling a crystal orientation of the gallium nitride, and without bonding the gallium nitride, as a unit, to the support member. In other embodiments, the number of crystals can be increased by a process that includes annealing a region in which the crystals are present, etching the region to remove crystals having an orientation other than the selected orientation, and/or growing the crystals having the selected orientation.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 21, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Anthony Lochtefeld, Hugues Marchand
  • Publication number: 20150021621
    Abstract: This disclosure provides a transistor device formed on a wide band gap substrate. The transistor device includes a channel layer and a gate structure physically coupled to the channel layer. The gate structure can be formed on the channel layer using an epitaxial process instead of a lithographic process, thereby providing a mechanism to build small semiconductor features that are smaller than a resolution of the state-of-the-art lithographic process and reducing the amount of impurities between the channel layer and the gate structure.
    Type: Application
    Filed: July 21, 2014
    Publication date: January 22, 2015
    Inventors: Bunmi T. ADEKORE, Hugues MARCHAND
  • Publication number: 20140367698
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 18, 2014
    Applicant: The Regents of the University of California
    Inventors: Hugues Marchand, Brendan J. Moran, Umesh K. Mishra, James S. Speck
  • Patent number: 8525230
    Abstract: A field effect transistor including a compositionally graded group-III nitride layer on a silicon substrate.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: September 3, 2013
    Assignee: The Regents of the University of California
    Inventors: Hugues Marchand, Brendan J. Moran, Umesh K. Mishra, James S. Speck
  • Publication number: 20120068191
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Application
    Filed: November 29, 2011
    Publication date: March 22, 2012
    Applicant: The Regents of the University of California
    Inventors: Hugues Marchand, Brendan J. Moran, Umesh K. Mishra, James S. Speck
  • Publication number: 20110147772
    Abstract: Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. The method can further include forming a volume of gallium nitride carried by the crystals, with the selected orientation of the crystals at least partially controlling a crystal orientation of the gallium nitride, and without bonding the gallium nitride, as a unit, to the support member. In other embodiments, the number of crystals can be increased by a process that includes annealing a region in which the crystals are present, etching the region to remove crystals having an orientation other than the selected orientation, and/or growing the crystals having the selected orientation.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 23, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Anthony Lochtefeld, Hugues Marchand
  • Publication number: 20110108886
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Application
    Filed: October 11, 2010
    Publication date: May 12, 2011
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Hugues Marchand, Brendan J. Moran, Umesh K. Mishra, James S. Speck
  • Patent number: 7816764
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: October 19, 2010
    Assignee: The Regents of the University of California
    Inventors: Hugues Marchand, Brendan Jude Moran
  • Patent number: 7687888
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: March 30, 2010
    Assignee: The Regents of the University of California
    Inventors: Hugues Marchand, Brendan Jude Moran