Patents by Inventor Hugues Thiebeauld De La Crouee

Hugues Thiebeauld De La Crouee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11036891
    Abstract: In a general aspect, a test method can include: acquiring a plurality of value sets, each comprising values of a physical quantity or of logic signals, linked to the activity of a circuit to be tested when executing distinct cryptographic operations applied to a same secret data, for each value set, counting occurrence numbers of the values of the set, for each operation and each of the possible values of a part of the secret data, computing a partial result of operation, computing sums of occurrence numbers, each sum being obtained by adding the occurrence numbers corresponding to the operations which when applied to a same possible value of the part of the secret data, provide a partial operation result having a same value, and analyzing the sums of occurrence numbers to determine the part of the secret data.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 15, 2021
    Assignee: ESHARD
    Inventors: Benoît Feix, Hugues Thiebeauld de la Crouee
  • Patent number: 10505711
    Abstract: In a general aspect, a method for executing a target operation combining a first input data with a second input data, and providing an output data can include generating at least two pairs of input words each comprising a first input word and a second input word and applying to each pair of input words a same derived operation providing an output word including a part of the output data resulting from the application of the target operation to first and second input data parts present in the pair of input words, and a binary one's complement of the output data part.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: December 10, 2019
    Assignee: ESHARD
    Inventors: Hugues Thiebeauld de La Crouee, Antoine Wurcker
  • Patent number: 10491372
    Abstract: A method for executing, by a circuit, an operation combining first and second input data and providing an output data of the same size, may include generating from the first input data a first input set including all possible data in relation to a size of the first data, generating from the second input data a second input set including all possible data in relation to a size of the second data, and applying the operation to each pair of data including a data of the first input set and a data of the second input set, an output set of the operation including data resulting from the application of the operation to each of the pairs of data.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 26, 2019
    Assignee: ESHARD
    Inventors: Antoine Wurcker, Hugues Thiebeauld De La Crouee
  • Patent number: 10439797
    Abstract: A method for executing by a circuit a bit permutation operation by which bits of an input data are mixed to obtain an output data including at least two words, may include: generating a mask set including mask parameters, the mask set having one word column per word of the input data; generating an input set by combining the input data with each mask parameter of the mask set by Exclusive OR (XOR) operations; and computing an output set including output data resulting from the application of the bit permutation operation to each data in the input set, where the mask set may be generated such that the output set includes columns of output words, and each word column of the mask set an the output set including a same number of occurrences of all possible values of one input data word and respectively one output word.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 8, 2019
    Assignee: ESHARD
    Inventors: Antoine Wurcker, Hugues Thiebeauld de la Crouee
  • Patent number: 10419206
    Abstract: A test method of a circuit, comprising, acquiring value sets including values of a physical quantity or of logic signals, linked to the activity of a circuit to be tested when the circuit executes an operation of an operation set of distinct cryptographic operations applied to a same secret data, selecting at least two subsets of values in each value set, for each value set and each value subset, counting occurrence numbers of values of the subset, for each value set, forming all possible n-tuples associating together one of the occurrence numbers of each value subset of the value set, and computing a combined occurrence number for each n-tuple of the value set, to form an occurrence number set for the value set, and analyzing the occurrence number sets to determine the part of the secret data.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: September 17, 2019
    Assignee: ESHARD
    Inventors: Hugues Thiebeauld de la Crouee, Georges Gagnerot
  • Patent number: 10320555
    Abstract: A test method can include: acquiring a plurality of value sets including measurements or signals corresponding with activity of a circuit when executing a set of cryptographic operations on secret data, for each value set, selecting at least two subsets of values, computing combined values and counting occurrence numbers of values transformed by a first surjective function applied to the combined values, for each operation and each possible value of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets by adding the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value of the possible values of the part of the secret data, provide a partial operation result having a same transformed value by a second surjective function, and determine the part of the secret data from the cumulative occurrence number sets.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: June 11, 2019
    Assignee: ESHARD
    Inventors: Hugues Thiebeauld De La Crouee, Antoine Wurcker
  • Patent number: 10243729
    Abstract: In a general aspect, a test method can include acquiring a plurality of value sets, each including values of a physical quantity or of logic signals, linked to the activity of a circuit to be tested when executing distinct cryptographic operations applied to a same secret data, for each value set, counting occurrence numbers of the values of the set, for each operation and each of the possible values of a part of the secret data, computing a partial result of operation, computing sums of occurrence numbers, each sum being obtained by adding the occurrence numbers corresponding to the operations which when applied to a same possible value of the part of the secret data, provide a partial operation result having a same value, and analyzing the sums of occurrence numbers to determine the part of the secret data.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 26, 2019
    Assignee: ESHARD
    Inventor: Hugues Thiebeauld De La Crouee
  • Patent number: 10230521
    Abstract: The present invention relates to a test method of a circuit, comprising: acquiring a plurality of value sets comprising values of a physical quantity linked to the activity of a circuit to be tested when the circuit executes an operation of a set of distinct cryptographic operations applied to a secret data, selecting at least a first subset in each value set, for each value set, counting by a processing unit occurrence numbers of values transformed by a first surjective function applied to the values of the first subset of the value set, to form an occurrence number set for the value set, for each operation of the operation set, and each of the possible values of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets by adding the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value or equivalent value of the possible values of the part of the secret data, provide a partial operation result having
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 12, 2019
    Assignee: Eshard
    Inventors: Antoine Wurcker, Hugues Thiebeauld De La Crouee, Christophe Clavier
  • Publication number: 20190057228
    Abstract: In a general aspect, a test method can include: acquiring a plurality of value sets, each comprising values of a physical quantity or of logic signals, linked to the activity of a circuit to be tested when executing distinct cryptographic operations applied to a same secret data, for each value set, counting occurrence numbers of the values of the set, for each operation and each of the possible values of a part of the secret data, computing a partial result of operation, computing sums of occurrence numbers, each sum being obtained by adding the occurrence numbers corresponding to the operations which when applied to a same possible value of the part of the secret data, provide a partial operation result having a same value, and analyzing the sums of occurrence numbers to determine the part of the secret data.
    Type: Application
    Filed: August 20, 2018
    Publication date: February 21, 2019
    Inventors: Benoît Feix, Hugues Thiebeauld de la Crouee
  • Patent number: 10147033
    Abstract: The electronic component comprises: reference-obtaining means for obtaining a physical magnitude referred to as a reference magnitude, which magnitude is dynamically adjustable and representative of the expected activity of said component; comparator means suitable for comparing said reference magnitude with a magnitude of the same type representative of the real activity of said component; and detector means suitable for detecting an attack as a function of the result of said comparison.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: December 4, 2018
    Assignee: OBERTHUR TECHNOLOGIES
    Inventors: Nicolas Morin, Hugues Thiebeauld De La Crouee
  • Publication number: 20170373829
    Abstract: A method for executing, by a circuit, an operation combining first and second input data and providing an output data of the same size, may include generating from the first input data a first input set including all possible data in relation to a size of the first data, generating from the second input data a second input set including all possible data in relation to a size of the second data, and applying the operation to each pair of data including a data of the first input set and a data of the second input set, an output set of the operation including data resulting from the application of the operation to each of the pairs of data.
    Type: Application
    Filed: June 28, 2017
    Publication date: December 28, 2017
    Inventors: Antoine WURCKER, Hugues THIEBEAULD DE LA CROUEE
  • Publication number: 20170373832
    Abstract: A method for executing by a circuit a bit permutation operation by which bits of an input data are mixed to obtain an output data including at least two words, may include: generating a first mask set including mask parameters, the mask set having one word column per word of the input data, each word column comprising a same number of occurrences of all possible values of one input data word in relation to a size of the input data word; generating an input set by combining the input data with each mask parameter of the first mask set by Exclusive OR (XOR) operations; and computing an output set including output data resulting from the application of the bit permutation operation to each data in the input set, where the first mask set may be generated such that the output set includes columns of output words, and each output word column including a same number of occurrences of all possible values of one output word in relation with a size of the output word.
    Type: Application
    Filed: June 28, 2017
    Publication date: December 28, 2017
    Inventors: Antoine WURCKER, Hugues THIEBEAULD DE LA CROUEE
  • Publication number: 20170244548
    Abstract: A test method can include: acquiring a plurality of value sets including measurements or signals corresponding with activity of a circuit when executing a set of cryptographic operations on secret data, for each value set, selecting at least two subsets of values, computing combined values and counting occurrence numbers of values transformed by a first surjective function applied to the combined values, for each operation and each possible value of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets by adding the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value of the possible values of the part of the secret data, provide a partial operation result having a same transformed value by a second surjective function, and determine the part of the secret data from the cumulative occurrence number sets.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 24, 2017
    Inventors: Hugues THIEBEAULD DE LA CROUEE, Antoine WURCKER
  • Publication number: 20170244550
    Abstract: The present invention relates to a test method of a circuit, comprising: acquiring a plurality of value sets comprising values of a physical quantity linked to the activity of a circuit to be tested when the circuit executes an operation of a set of distinct cryptographic operations applied to a secret data, selecting at least a first subset in each value set, for each value set, counting by a processing unit occurrence numbers of values transformed by a first surjective function applied to the values of the first subset of the value set, to form an occurrence number set for the value set, for each operation of the operation set, and each of the possible values of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets by adding the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value or equivalent value of the possible values of the part of the secret data, provide a partial operation result having
    Type: Application
    Filed: February 22, 2017
    Publication date: August 24, 2017
    Inventors: Antoine WURCKER, Hugues THIEBEAULD DE LA CROUEE, Christophe CLAVIER
  • Publication number: 20170244552
    Abstract: In a general aspect, a method for executing a target operation combining a first input data with a second input data, and providing an output data can include generating at least two pairs of input words each comprising a first input word and a second input word and applying to each pair of input words a same derived operation providing an output word including a part of the output data resulting from the application of the target operation to first and second input data parts present in the pair of input words, and a binary one's complement of the output data part.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 24, 2017
    Inventors: Hugues THIEBEAULD DE LA CROUEE, Antoine WURCKER
  • Publication number: 20170244551
    Abstract: In a general aspect, a method for executing, by a circuit, an operation receiving an input data and providing an output data includes: selecting a substitution element in a substitution table as a function of the input data or an intermediary data, the substitution element being a first data set, each substitution element in the substitution table being selectable as a function of an input substitution data being a data set, and providing the first data set as an intermediary or final result of the operation, the first data set including the output data, and being such that in a set of transformed data resulting from a surjective function applied to the first data set, the transformed output data occurs with a probability equal to the probability of occurrence of each transformed data resulting from the application of the surjective function to the other data in the first data set.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 24, 2017
    Inventor: Hugues THIEBEAULD DE LA CROUEE
  • Publication number: 20170244549
    Abstract: A test method for a circuit can include: acquiring a plurality of value sets including values corresponding to activity of the circuit when the circuit executes an operation of an operation set of distinct cryptographic operations applied to a same secret data, selecting at least two subsets of values in each value set, for each value set and each value subset, counting occurrence numbers of values transformed by a respective first surjective function applied to the values of the subset, for each value set, forming all possible n-tuples associating together one of the occurrence numbers of each value subset of the value set, and computing a combined occurrence number for each n-tuple of the value set by multiplying together the occurrence numbers associated by the n-tuple, to form an occurrence number set for the value set, for each operation of the operation set, and each possible value of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets, obtained b
    Type: Application
    Filed: February 22, 2017
    Publication date: August 24, 2017
    Inventors: Hugues THIEBEAULD DE LA CROUEE, Georges GAGNEROT
  • Publication number: 20170244547
    Abstract: In a general aspect, a test method can include acquiring a plurality of value sets, each including values of a physical quantity or of logic signals, linked to the activity of a circuit to be tested when executing distinct cryptographic operations applied to a same secret data, for each value set, counting occurrence numbers of the values of the set, for each operation and each of the possible values of a part of the secret data, computing a partial result of operation, computing sums of occurrence numbers, each sum being obtained by adding the occurrence numbers corresponding to the operations which when applied to a same possible value of the part of the secret data, provide a partial operation result having a same value, and analyzing the sums of occurrence numbers to determine the part of the secret data.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 24, 2017
    Inventor: Hugues THIEBEAULD DE LA CROUEE
  • Patent number: 8788847
    Abstract: A secure data processing method includes the following steps: padding (E206) a memory area (MAC?) with a pad value (A); writing (E208) a first datum in the memory area (MAC?); in the area, reading (E210) a second datum with at least one part of the first datum as it was written in the memory area (MAC?); and executing an operation (E210) using the second datum.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: July 22, 2014
    Assignee: Oberthur Technologies
    Inventors: Hugues Thiebeauld De La Crouee, Christophe Giraud
  • Patent number: 8707424
    Abstract: A method for making secure execution of a computer program includes the following steps: stacking a predetermined value in a pile of instructions of the program; and stack popping the pile, the stack popping step being adapted, as the case may be, to enable detection of an anomalous execution.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: April 22, 2014
    Assignee: Oberthur Technologies
    Inventors: Jean-Bernard Fischer, Hugues Thiebeauld De La Crouee