Patents by Inventor Hui-An HAN

Hui-An HAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240312792
    Abstract: A method of manufacturing a semiconductor device includes forming a gate dielectric layer over a channel region, and forming a first conductive layer over the gate dielectric layer. The method further includes forming a protective layer at a surface region of the first conductive layer by implanting a dopant into the surface region of the first conductive layer. The dopant is selected from a group consisting of boron, silicon, carbon, and nitrogen. The method also includes forming a metallic layer by applying a metal containing gas on the protective layer, and removing the metallic layer by a wet etching operation using a solution.
    Type: Application
    Filed: May 22, 2024
    Publication date: September 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-An HAN, Ding-I LIU, Yuh-Ta FAN, Kai-Shiung HSU
  • Patent number: 12020947
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-An Han, Ding-I Liu, Yuh-Ta Fan, Kai-Shiung Hsu
  • Publication number: 20210351041
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Inventors: Hui-An HAN, Ding-I LIU, Yuh-Ta FAN, Kai-Shiung HSU
  • Patent number: 11069534
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-An Han, Ding-I Liu, Yuh-Ta Fan, Kai-Shiung Hsu
  • Publication number: 20200135868
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 30, 2020
    Inventors: Hui-An HAN, Ding-I LIU, Yuh-Ta FAN, Kai-Shiung HSU