Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

Abstract: An integrated circuit includes a first power rail and a second power rail extending in a first direction, and a first power grid stub connected to the first power rail through a first via-connector. The integrated circuit also includes a first vertical conducting line extending in a second direction in a circuit cell between a first vertical cell boundary and a second vertical cell boundary. The first vertical conducting line and the first power grid stub are in a same metal layer and aligned with each other along the second direction.

Abstract: Disclosed is a flash memory card without a substrate, primarily comprising a memory chip component, a controller chip disposed on the memory chip, and an encapsulant encapsulating both chips. Formed on an active surface and a back surface of the memory chip component are a first RDL (redistribution layer) and a second RDL respectively. A plurality of TSVs (through silicon vias) penetrate from the active surface to the back surface to electrically connect both RDLs. A plurality of contacting fingers are disposed on the back surface of the memory chip component and electrically connected with the second RDL. Additionally, the encapsulant has a card appearance with one surface of each contacting finger to be exposed. Accordingly, the flash memory card can save conventional substrate structure with better reliability and efficiency for packaging processes.

Abstract: Disclosed is a multi-chip memory package with a small substrate by using a die pad having an opening to substitute the chip-carrying function of a conventional substrate so that substrate dimension can be reduced. A substrate is attached under the die pad. A first chip is disposed on the substrate located inside the opening. A second chip is disposed on the die pad. An encapsulant encapsulates the top surface of the die pad, the top surface of the substrate, the first chip, and the second chip. The dimension of the substrate is smaller than the dimension of the encapsulant. In a preferred embodiment, a plurality of tie bars physically connect to the peripheries of the die pad and extend to the sidewalls of the encapsulant to have a plurality of insulated cut ends exposed from the encapsulant.

Abstract: Disclosed is a multi-chip package having leadframe-type contact fingers, primarily comprising a leadframe, a non-conductive tape, a first chip and a second chip disposed on the first chip. The leadframe includes a die paddle on which the first chip is disposed and a plurality of first contact fingers, moreover, at least a second contact finger is integrally extended from the die paddle and is located among the first contact fingers so that the first and second contact fingers are arranged in a row. The non-conductive tape is attached onto the first and second contact fingers conforming to the arranging row of the first contact fingers so that the second contact finger is mechanically fastened with the first contact fingers. An encapsulant encapsulates the first chip, the second chip and the non-conductive tape with a plated metal layer formed on the bottom surfaces of the first and second contact fingers and exposed from the encapsulant.

Abstract: A display panel comprising a substrate, a display array formed on the substrate, and a test circuit disposed on the substrate and comprising shorting bars, testing lines, a first and a second isolation layers, and a conductive structure. The shorting bars include a first short bar. The testing lines include a first testing line vertical with the first shorting bar and electrically connecting the display array. The first isolation layer is formed between the shorting bars and the testing lines. The second isolation layer is disposed on the shorting bars, the testing lines, and the first isolation layer and has a first and a second holes, which correspond to the first shorting bar. The second hole penetrates through the first isolation layer. The conductive structure is formed on the second isolation layer and electrically connects the first testing line and the first shorting bar through the first and second holes.

Abstract: A flexible printed circuit comprising a substrate, a plurality of function lines, and a plurality of first dummy lines. The substrate comprises at least two periphery areas and an intermediate area. Each periphery area comprises a first layout region, a second layout region and a first rough region disposed between the first and second layout regions. The intermediate area is disposed between the periphery areas. The function lines are disposed on the substrate and within the intermediate area. The first dummy lines are disposed on the substrate and within the first or second layout area.

Abstract: A printed circuit board (PCB) for a display preventing increase of thermal expansion. The PCB comprises a plurality of bonding regions and at least one opening. The bonding regions are disposed on the inner side of the PCB. The opening is disposed between two adjacent bonding regions.

Abstract: A bonding pad structure of a display device. A first conductive layer is formed overlying a substrate, a protection layer is formed overlying the substrate and the first conductive layer, and a second conductive layer is formed overlying the protection layer. An opening structure penetrates the second conductive layer and the protection layer to expose the first conductive layer. A third conductive layer is formed overlying the second conductive layer to contact the sidewall and bottom of the opening structure. Thus, the third conductive layer is electrically connected to the second conductive layer to provide a first electrical-connection path, and the third conductive layer is electrically connected to the first conductive layer to provide a second electrical-connection path.

Abstract: A display module includes a glass substrate, a first lead group, a second lead group, and a plurality of first dummy leads. The first lead group and the second lead group are disposed on a marginal area of the glass substrate. There is a flexible printed circuit (FPC) disposed on the first lead group and the second lead group after a first anisotropic conductive film (ACF) is applied thereon. The first dummy leads are disposed between the first lead group and the second lead group and also on the marginal area of the glass substrate. The first lead group and the second lead group are covered with the first ACF, and the first dummy leads are also covered by the first ACF to improve the performance of adhesion of the first ACF to the glass substrate.

Abstract: A thin film transistor (TFT) substrate includes a glass substrate, a thin film transistor, an electrode pad, and a conductive bump. The TFT and the electrode pad are formed on the glass substrate, and the electrode pad is used for electrically connecting with the thin film transistor. The conductive bump includes several insulating bumps and a conductive layer. The insulating bumps are formed on the electrode pad dividedly, and the conductive layer covers the top surfaces of the insulating bumps, the inward surfaces of the insulating bumps, and the electrode pad between the insulating bumps for electrically connecting with the electrode pad. The outward side surfaces of the insulating bumps are exposed out of the conductive layer.

Abstract: A liquid crystal display device includes a thin film transistor array disposed on a first region of a panel. An anisotropic conductive film bonds at least one integrated circuit chip and at least one other device, such as a FPC board, a TCP and a COF, to a second region of the panel.

Abstract: A display module includes a glass substrate, a first lead group, a second lead group, and a plurality of first dummy leads. The first lead group and the second lead group are disposed on a marginal area of the glass substrate. There is a flexible printed circuit (FPC) disposed on the first lead group and the second lead group after a first anisotropic conductive film (ACF) is applied thereon. The first dummy leads are disposed between the first lead group and the second lead group and also on the marginal area of the glass substrate. The first lead group and the second lead group are covered with the first ACF, and the first dummy leads are also covered by the first ACF to improve the performance of adhesion of the first ACF to the glass substrate.

Abstract: A thin film transistor (TFT) substrate includes a glass substrate, a thin film transistor, an electrode pad, and a conductive bump. The TFT and the electrode pad are formed on the glass substrate, and the electrode pad is used for electrically connecting with the thin film transistor. The conductive bump includes several insulating bumps and a conductive layer. The insulating bumps are formed on the electrode pad dividedly, and the conductive layer covers the top surfaces of the insulating bumps, the inward surfaces of the insulating bumps, and the electrode pad between the insulating bumps for electrically connecting with the electrode pad. The outward side surfaces of the insulating bumps are exposed out of the conductive layer.

Abstract: A display module includes a glass substrate, a first lead group, a second lead group, and a plurality of first dummy leads. The first lead group and the second lead group are disposed on a marginal area of the glass substrate. There is a flexible printed circuit (FPC) disposed on the first lead group and the second lead group after a first anisotropic conductive film (ACF) is applied thereon. The first dummy leads are disposed between the first lead group and the second lead group and also on the marginal area of the glass substrate. The first lead group and the second lead group are covered with the first ACF, and the first dummy leads are also covered by the first ACF to improve the performance of adhesion of the first ACF to the glass substrate.

Abstract: A display panel comprising a substrate, a display array formed on the substrate, and a test circuit disposed on the substrate and comprising shorting bars, testing lines, a first and a second isolation layers, and a conductive structure. The shorting bars include a first short bar. The testing lines include a first testing line vertical with the first shorting bar and electrically connecting the display array. The first isolation layer is formed between the shorting bars and the testing lines. The second isolation layer is disposed on the shorting bars, the testing lines, and the first isolation layer and has a first and a second holes, which correspond to the first shorting bar. The second hole penetrates through the first isolation layer. The conductive structure is formed on the second isolation layer and electrically connects the first testing line and the first shorting bar through the first and second holes.

Abstract: A thin film transistor (TFT) substrate includes a glass substrate, a thin film transistor, an electrode pad, and a conductive bump. The TFT and the electrode pad are formed on the glass substrate, and the electrode pad is used for electrically connecting with the thin film transistor. The conductive bump includes several insulating bumps and a conductive layer. The insulating bumps are formed on the electrode pad dividedly, and the conductive layer covers the top surfaces of the insulating bumps, the inward surfaces of the insulating bumps, and the electrode pad between the insulating bumps for electrically connecting with the electrode pad. The outward side surfaces of the insulating bumps are exposed out of the conductive layer.

Abstract: A bonding pad structure of a display device. A first conductive layer is formed overlying a substrate, a protection layer is formed overlying the substrate and the first conductive layer, and a second conductive layer is formed overlying the protection layer. An opening structure penetrates the second conductive layer and the protection layer to expose the first conductive layer. A third conductive layer is formed overlying the second conductive layer to contact the sidewall and bottom of the opening structure. Thus, the third conductive layer is electrically connected to the second conductive layer to provide a first electrical-connection path, and the third conductive layer is electrically connected to the first conductive layer to provide a second electrical-connection path.

Abstract: A flexible printed circuit comprising a substrate, a plurality of function lines, and a plurality of first dummy lines. The substrate comprises at least two periphery areas and an intermediate area. Each periphery area comprises a first layout region, a second layout region and a first rough region disposed between the first and second layout regions. The intermediate area is disposed between the periphery areas. The function lines are disposed on the substrate and within the intermediate area. The first dummy lines are disposed on the substrate and within the first or second layout area.

Abstract: A liquid crystal display panel module and a flexible printed circuit board thereof. The liquid crystal display panel module includes a substrate and the flexible printed circuit board connected with the substrate. The flexible printed circuit board includes a base, a lead, a passivation layer and an insulation layer. The lead is disposed on the base, and has a first end portion and a second end portion. The passivation layer covers the lead without covering the first end portion. The insulation layer is disposed at an interface between the passivation layer and the first end portion to cover part of the passivation layer and part of the first end portion.