Abstract: A method includes performing a first die-saw on a package structure includes forming a first and a second metal lead extending into a trench of a package structure, wherein the first and the second metal leads contact the side edges of contact pads that are in devices in the package structure. The first and the second metal leads are interconnected through a connecting metal portion. A pre-cut is performed to cut the connecting metal portion to separate the first and the second metal leads, wherein remaining portions of the connecting metal portion have edges after the pre-cut. A dielectric coating is formed over the first and the second metal leads. A die-saw is performed to saw apart the package structure, so that the first and the second dies are separated into separate piece. In each of the resulting pieces, the edges of the remaining portions of the connecting metal portion are covered by remaining portions of the first dielectric coating.

Abstract: A method includes performing a first die-saw on a package structure includes forming a first and a second metal lead extending into a trench of a package structure, wherein the first and the second metal leads contact the side edges of contact pads that are in devices in the package structure. The first and the second metal leads are interconnected through a connecting metal portion. A pre-cut is performed to cut the connecting metal portion to separate the first and the second metal leads, wherein remaining portions of the connecting metal portion have edges after the pre-cut. A dielectric coating is formed over the first and the second metal leads. A die-saw is performed to saw apart the package structure, so that the first and the second dies are separated into separate piece. In each of the resulting pieces, the edges of the remaining portions of the connecting metal portion are covered by remaining portions of the first dielectric coating.

Abstract: A method system for synchronizing a control chart of an SPC system and equipment performance has a chart model (22) with new chart properties; a method for calculating a control limit based on a statistical deviation, a synchronization frequency for setting a time for reviewing new data gathered by the SPC system, and a process catalog for categorizing all control charts that control the same process step, such that the control charts are organized for assignment of the same performance based control limit calculated by using statistics formed by data for control limit values of the control charts.

Abstract: A method and system for synchronizing a control chart of an SPC system and equipment performance has a chart model (22) with new chart properties; a method for calculating a control limit based on a statistical deviation, a synchronization frequency for setting a time for reviewing new data gathered by the SPC system, and a process catalog for categorizing all control charts that control the same process step, such that the control charts are organized for assignment of the same performance based control limit calculated by using statistics formed by data for control limit values of the control charts.

Abstract: A method is provided for forming multi-layer spacer (MLS) for flash EEPROM devices. A composite tetraethyl orthosilicate-silicon nitride (TEOS/Si3N4) layer is deposited over the floating gate and anisotropically etched to form the MLS. The resulting MLS is better controlled dimensionally with the attendant advantage, therefore, of better definition of gate and channel lengths in the memory cell for more predictable and better programming and erase performance of EEPROMs.

Abstract: A plasma etch method for forming a patterned layer first employs a substrate having formed therover a blanket microelectronic layer. There is also formed over the blanket microelectronic layer a patterned mask layer. There is then etched, while employing a first plasma etch method which employs the patterned mask layer as an etch mask layer, the blanket microelectronic layer to form a partially etched blanket microelectronic layer. There is then etched, while employing a second plasma etch method which employs the patterned mask layer as an etch mask layer, the partially etched blanket microelectronic layer to form a patterned microelectronic layer. Within the present invention, the first plasma etch method employs a higher bias voltage than the second plasma etch method.

Abstract: A method for eliminating metal line corrosion for semiconductor packages where exposed metal lines are exposed to the atmosphere for an extended period of time. A passivation layer is deposited over the active die of the semiconductor package, a layer of polymer film is deposited over the passivation layer and over the exposed conducting lines. At the time that the semiconductor package must be tested, including testing for corrosion of the exposed metal lines, the polymer layer is removed and the molding compound is applied. The semiconductor package is now tested. The added step of depositing a layer of polymer film has protected the interconnecting conducting lines from corrosion.

Abstract: A method for forming a CMOS image sensor spacer structure. A polysilicon gate electrode is formed on a substrate; a thin layer of first dielectric is deposited over the exposed surfaces of the gate electrode and the top of the substrate. Next a second layer of dielectric is deposited after which etching is performed to create the electrode spacer. The deposited second layer of dielectric serves as an etch stop and prevents damage to the substrate surface between spacers of the gate electrodes. An alternate method uses a thin ply layer as the stop layer and, in so doing, source/drain damage caused by the white pixel problem.

Abstract: A method is provided for forming multi-layer spacer GELS) for flash EEPROM devices. A composite tetraethyl orthosilicate-silicon nitride (TEOS/Si.sub.3 N.sub.4) layer is deposited over the floating gate and anisotropically etched to form the MLS. The resulting MLS is better controlled dimensionally with the attendant advantage, therefore, of better definition of gate and channel lengths in the memory cell for more predictable and better programming and erase performance of EEPROMS.