Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.

Abstract: A wheel cylinder adjuster includes a rotary unit and a driving unit connected with the rotary unit. The rotary unit includes a rotary disk, a fixing member, two positioning members, a resilient ring, a restriction member and a clip. The rotary disk has a guide groove designed in a shape containing two semi-ovals. Two stepped slots are defined through the fixing member and the positioning members extend through the two stepped slots. Each positioning member has a guide tip which is located in the guide groove. The resilient ring is mounted to the positioning members and the tubular portion. The rotary disk is rotated and the guide tips of the positioning members more in the stepped slots so as to adjust the distance between the positioning members so as to be operated to different sizes of the wheel cylinders.

Abstract: A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.

Abstract: A programming method, a reading method and an operating system for a memory are provided. The programming method includes the following steps. A data is provided. A parity generation is performed to obtain an error-correcting code (ECC). The memory is programmed to record the data and the error-correcting code. The data is transformed before performing the parity generation, such that a hamming distance between two codes corresponding to two adjacent threshold voltage states in the data to be performed the parity generation is 1.

Abstract: Disclosed are control circuits capable of auto-configuring two LED arrays either in parallel when the two LED arrays are operating off of 100±20% V AC voltage sources or in series when the two LED arrays are operating off of 200±20% V AC voltage sources according to the detection of the AC input voltage magnitude. The disclosed control circuits, ruling over the parallel or series configuration of the two LED arrays, could be implemented in discrete forms or as integrated circuits (IC).

Abstract: An organic light emitting diode display device and a manufacturing method thereof are provided. The organic light emitting diode display device includes a first flexible substrate, a second flexible substrate, a first barrier layer, a second barrier layer, an organic light emitting diode element, and a metal enclosing wall. The first barrier layer is disposed on the first flexible substrate, and the second barrier layer is disposed on the second flexible substrate. The organic light emitting diode element is disposed between the first barrier layer and the second barrier layer. The metal enclosing wall connects the first flexible substrate to the second flexible substrate and surrounds the organic light emitting diode element.

Abstract: A display apparatus includes a back plate having a rear wall and a peripheral wall that cooperatively define an accommodation space, a light guide plate disposed in the accommodation space, a display panel disposed in the accommodation space forwardly of the light guide plate, a plurality of stacked optical films disposed between the light guide plate and the display panel, and a panel fixing device including a first limiting unit and a second limiting unit that cooperate with each other to clamp and fix a peripheral edge portion of the display panel therebetween.

Abstract: A pair of glasses includes a front frame, at least one lens, two temples, and two elongated couplers. The front frame is formed with two connection blocks at its two opposite ends. The front side of each connection block defines a cut. The rear side of each connection block is provided with two spaced lugs. The lens defines a cut corresponding to the cut of one connection block of the front frame. The front end of each temple is provided with a pivot pin that can be detachably fitted in the through-holes of the lugs of the connection block and the rear end of the elongated coupler, so that each temple is foldable relative to the front frame. The front end of each elongated coupler is provided with a hooked portion that can be detachably fitted into the cuts of the lens and connection block to install the lens.

Abstract: A power management method for a computer system is provided. The power management method includes: obtaining a system power consumption; determining whether the system power consumption is greater than a first safe operating point; when the system power consumption is greater than the first safe operating point, controlling a CPU and a graphics processing unit (GPU) to activate a frequency reduction mechanism according to a first adjustment sequence; when the system power consumption is not greater than the first safe operating point, determining whether the system power consumption is smaller than a second safe operating point; and when the system power consumption is smaller than the second safe operating point, controlling the CPU and the GPU to deactivate the frequency reduction mechanism according to a second adjustment sequence. The second adjustment sequence is reverse to the first adjustment sequence.

Abstract: A semiconductor structure includes a first gate-all-around (GAA) structure configured to form a first circuit and a second GAA structure configured to form a second circuit similar to the first circuit. The first GAA structure and the second GAA structure have a same of at least one of the following exemplary features: a number of GAA devices in which current flows from a first oxide definition (OD) region to a second OD region; a number of GAA devices in which current flows from the second OD region to the first OD region; a number of first OD region contact elements; a number of second OD region contact elements.

Abstract: A circuit for voltage detection and protection comprises a first block, a first voltage detector, a second block and a second voltage detector. The first block receives a first voltage supply. The first voltage detector detects the first voltage supply and generates a first detecting signal when detecting the first voltage supply level is out of the first operating voltage range. The second block receives a second voltage supply. The second voltage detector detects the second voltage supply and generates a second detecting signal when detecting the second voltage supply level is out of the second operating voltage range. The first block performs a protection operation on the circuit when monitoring at least one of the first and second detecting signals.

Abstract: A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.

Abstract: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.

Abstract: A method of epitaxial growth of a germanium film on a silicon substrate includes the steps of: providing a silicon substrate, placing the silicon substrate in a vacuum chamber, heating the silicon substrate to a temperature that is lower than 300° C., and forming a monocrystalline germanium film on the silicon substrate in the vacuum chamber, by employing an electron cyclotron resonance chemical vapor deposition (ECR-CVD) approach, wherein the step of forming a monocrystalline germanium film on the silicon substrate in the vacuum chamber further includes dissociating a reaction gas introduced into the vacuum chamber in utilization of a microwave source, such that the monocrystalline germanium film is deposited on the silicon substrate, and wherein the reaction gas includes at least germane (GeH4) and hydrogen gas (H2).

Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. Alternatively, the output buffer delay is variable. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and can include a first delay circuit that generates the first timing signal with a first delay, and a second delay circuit that generates the second timing signal with a second delay that correlates with the output buffer delay.

Abstract: A SCARA arm includes a base, a first arm, a second arm, a third linear shaft motor, and a fourth shaft motor. On the base is disposed a first shaft motor. The first arm is connected to and driven by the first shaft motor rotate in a horizontal direction. The second arm is fixed to a second shaft motor which is connected to the first arm to rotate the second arm in the horizontal direction. The third linear shaft motor includes a linear motor stator which extends in a vertical direction and is fixed to the second arm, and a linear motor mover which is sleeved onto the linear motor stator and movable along the vertical direction. The fourth shaft motor is drivingly connected to the linear motor mover and a rotary shaft, respectively, and another end of the rotary shaft is inserted out of the second arm.

Abstract: A solar panel assembly with a lighting pattern includes a solar panel and an energy storage device. An electroluminescence layer is disposed on a light receiving face of the solar panel. The electroluminescence layer includes a plurality through-holes. The number and the overall area of the plurality of through-holes are configured to permit incident light rays entering the electroluminescence layer to activate the solar panel to proceed with optical-electrical conversion, providing a light receiving effect and a light emitting effect on the same area of the solar panel. A patterned light-transmittable layer is coated on a face of the electroluminescence layer.

Abstract: A method for monitoring data error status of a memory device includes generating, by a memory controller, a data status indication code indicating error status of a data chunk transmitted by the memory controller and outputting, by the memory controller, the data status indication code to a user interface.

Abstract: A tube expander with positioning structure includes a base, a tube clamp, a positioning device, and an adjusting thread rod. Therein, the base has a body and a neck. The body has a guiding groove and the neck is inserted with a rotating thread rod capable of vertically moving. An expanding cone facing the guiding groove is on one end of the rotating thread rod. The tube clamp having tube bores is slidingly disposed in the guiding groove. The positioning device is on one side of the guiding groove, thereby engaging and positioning the tube clamp and positioning the tube bores under the expanding cone. The adjusting thread rod is pivotally disposed on the body for fastening the tube clamp.

Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state. Retention check logic executes to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.