Patents by Inventor Hui-Chu Lin

Hui-Chu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190331631
    Abstract: A biosensor and a biological detection method are provided. The biosensor includes a substrate, a plurality of first and second electrodes in a strip shape, a material layer and a capture antibody. The substrate has a sampling region and a measuring region connected to the sampling region. The first and second electrodes are disposed on the substrate in the measuring region, and the first and second electrodes are arranged alternately with each other, wherein the first electrodes are connected in parallel with each other, and the second electrodes are connected in parallel with each other.
    Type: Application
    Filed: April 30, 2019
    Publication date: October 31, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Hui-Chu Hsieh, Wen-Pin Hsieh, Nien-Jen Chou, Hui-Ju Shen, Hui-Ling Peng, Jing-Tsyr Lin
  • Publication number: 20190161430
    Abstract: A series of novel bis(hydroxymethyl) alkanoate derivatives of curcuminoids were designed, and synthesized, which show anticancer activity, and in particular to breast cancer, colon cancer, and prostate cancer.
    Type: Application
    Filed: June 2, 2017
    Publication date: May 30, 2019
    Inventors: SHENG-CHU KUO, KUO-HSIUNG LEE, CHANG-HAI TSAI, MIN-TSANG HSIEH, LING-CHU CHANG, HSIN-YI HUNG, HUI-YI LIN, JAI-SING YANG
  • Patent number: 9478669
    Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: October 25, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: I-Wei Wu, I-Min Lu, Wei-Chih Chang, Hui-Chu Lin, Yi-Chun Kao, Kuo-Lung Fang
  • Patent number: 8980704
    Abstract: A manufacturing method of a thin film transistor includes hard-baking and etching processes for a stop layer. Two through holes are exposed and developed in a photoresistor layer, in which a distance between the two through holes is substantially equal to the channel length of the thin film transistor. Further, the etching stop layer is dry-etched to obtain the thin film transistor having an expected channel length.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: March 17, 2015
    Assignee: Ye Xin Technology Consulting Co., Ltd.
    Inventors: I-Wei Wu, I-Min Lu, Wei-Chih Chang, Hui-Chu Lin, Yi-Chun Kao, Kuo-Lung Fang
  • Publication number: 20150056761
    Abstract: A manufacturing method of a thin film transistor includes hard-baking and etching processes for a stop layer. Two through holes are exposed and developed in a photoresistor layer, in which a distance between the two through holes is substantially equal to the channel length of the thin film transistor. Further, the etching stop layer is dry-etched to obtain the thin film transistor having an expected channel length.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 26, 2015
    Inventors: I-WEI WU, I-MIN LU, WEI-CHIH CHANG, HUI-CHU LIN, YI-CHUN KAO, KUO-LUNG FANG
  • Publication number: 20150053974
    Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 26, 2015
    Inventors: I-WEI WU, I-MIN LU, WEI-CHIH CHANG, HUI-CHU LIN, YI-CHUN KAO, KUO-LUNG FANG
  • Patent number: 8497150
    Abstract: This invention discloses a defect isolation method for thin-film solar cell having at least a defect therein. The thin-film solar cell comprises a substrate, a front electrode layer, an absorber layer and a back electrode layer stacked in such a sequence. The defect isolation method includes the steps of: detecting at least a defect formed in thin-film solar cell and acquiring the positions of the defects, and applying a laser light to scribe the outer circumference of the defects according to the positions of the defects so as to form at least an isolation groove having a closed-curve configuration.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: July 30, 2013
    Assignee: Nexpower Technology Corp.
    Inventors: Yung-Yuan Chang, Hui-Chu Lin
  • Publication number: 20110036393
    Abstract: The present invention discloses a thin film solar cell module and a manufacturing method thereof. The thin film solar cell comprises, from bottom to top, a first substrate, a first electrode, an absorber layer, and a second electrode layer. A first current output region formed at the positive electrode of the thin film solar cell module. A first current output element is disposed in the first current output region, and the absorber layer further comprises at least a first gap which is disposed in the first current output region to increase the contact between the first electrode layer and the second electrode layer. The useless current, the resistance and the heat generated there are reduced. The heat generated there is also reduced.
    Type: Application
    Filed: August 13, 2010
    Publication date: February 17, 2011
    Inventors: Chia-Yu Chen, Hui-Chu Lin, Chien-Chung Bi
  • Publication number: 20100087025
    Abstract: This invention discloses a defect isolation method for thin-film solar cell having at least a defect therein. The thin-film solar cell comprises a substrate, a front electrode layer, an absorber layer and a back electrode layer stacked in such a sequence. The defect isolation method includes the steps of: detecting at least a defect formed in thin-film solar cell and acquiring the positions of the defects, and applying a laser light to scribe the outer circumference of the defects according to the positions of the defects so as to form at least an isolation groove having a closed-curve configuration.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 8, 2010
    Inventors: Yung-Yuan Chang, Hui-Chu Lin
  • Publication number: 20100084015
    Abstract: This invention discloses a thin-film solar cell, provided with a plurality of unit cells, comprising a substrate, a front electrode layer, an absorber layer and a back electrode layer stacked in such a sequence. The thin-film solar cell further includes at least a defect formed at least in the back electrode layer, and the defect has at least an isolation groove of a closed curve formed around the defect.
    Type: Application
    Filed: September 28, 2009
    Publication date: April 8, 2010
    Inventors: Yung-Yuan CHANG, Hui-Chu Lin
  • Patent number: 6926932
    Abstract: A method for forming a silicon oxide layer in the production of the polysilicon film transistor is disclosed. A plasma surface treatment is performed over a substrate after an amorphous silicon layer has been formed on the substrate by PECVD to transform a portion of the amorphous silicon layer into a superficial oxide layer.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: August 9, 2005
    Assignee: Toppoly Optoelectronics Corp.
    Inventor: Hui-Chu Lin
  • Patent number: 6869834
    Abstract: The present invention provides a method of forming a low temperature polysilicon thin film transistor (LTPS TFT). A polysilicon layer including a channel region is formed first. A first and a second plasma enhanced chemical vapor deposition processes are sequentially performed to form a composite gate insulating layer composed of a TEOS-based silicon oxide layer and a silicon nitride layer on the channel region. Finally a gate electrode and a source/drain of the low temperature polysilicon thin film transistor are formed.
    Type: Grant
    Filed: February 16, 2003
    Date of Patent: March 22, 2005
    Assignee: Toppoly Optoelectronics Corp.
    Inventor: Hui-Chu Lin
  • Publication number: 20050059191
    Abstract: First, a substrate with a polysilicon film is provided. Then, a gate insulating layer and a gate are formed on the polysilicon film in sequence. An ion implantation process is performed to form a source and a drain around the gate. After that, a first plasma enhanced chemical vapor deposition (PECVD) process is performed to form a silicon nitride layer over the substrate and the gate. A second plasma enhanced chemical vapor deposition process is then performed to form a TEOS based silicon oxide layer on the silicon nitride layer. A photo-etching process follows to form a contact hole extending through to the source and drain respectively. Then, a conductive layer is filled into the contact holes and electrically connected to the source and drain.
    Type: Application
    Filed: September 17, 2003
    Publication date: March 17, 2005
    Inventor: Hui-Chu Lin
  • Publication number: 20050059192
    Abstract: First, a substrate with a polysilicon film is provided. Then, a gate insulating layer and a gate are formed on the polysilicon film in sequence. An ion implantation process is performed to form a source and a drain around the gate. After that, a first plasma enhanced chemical vapor deposition (PECVD) process is performed to form a silicon nitride layer over the substrate and the gate. A second plasma enhanced chemical vapor deposition process is then performed to form a TEOS based silicon oxide layer on the silicon nitride layer. A photo-etching process follows to form a contact hole extending through to the source and drain respectively. Then, a conductive layer is filled into the contact holes and electrically connected to the source and drain.
    Type: Application
    Filed: September 17, 2003
    Publication date: March 17, 2005
    Inventor: Hui-Chu Lin
  • Publication number: 20050025906
    Abstract: A method for improving uniformity of a film in a plasma enhanced chemical vapor deposition system in a deposition chamber includes the following steps before a deposition procedure. Firstly, a cleaning procedure is performed to remove particles adhered onto an internal wall of the deposition chamber. Then, a pre-deposition procedure is performed to isolate contaminants generated during the clearing procedure. Afterward, a specified gas is introduced into the deposition chamber so as to stabilize a condition inside the deposition chamber.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 3, 2005
    Inventors: Hui-Chu Lin, Wen-Cheng Lu
  • Publication number: 20040241341
    Abstract: A method for forming a silicon oxide layer in the production of the polysilicon film transistor is disclosed. A plasma surface treatment is performed over a substrate after an amorphous silicon layer has been formed on the substrate by PECVD to transform a portion of the amorphous silicon layer into a superficial oxide layer.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Inventor: Hui-Chu Lin
  • Publication number: 20040072392
    Abstract: The present invention provides a method of forming a low temperature polysilicon thin film transistor (LTPS TFT). A polysilicon layer including a channel region is formed first. A first and a second plasma enhanced chemical vapor deposition processes are sequentially performed to form a composite gate insulating layer composed of a TEOS-based silicon oxide layer and a silicon nitride layer on the channel region. Finally a gate electrode and a source/drain of the low temperature polysilicon thin film transistor are formed.
    Type: Application
    Filed: February 16, 2003
    Publication date: April 15, 2004
    Inventor: Hui-Chu Lin