Abstract: A display panel includes a substrate, a plurality of conductive components on a surface of the substrate, a plurality of light-emitting diodes. The conductive components are on a surface of the substrate and spaced apart from each other. Each conductive component includes a first conductive part and a second conductive part. The second conductive part is electrically connected to the first conductive part. A projection of the second conductive part on the surface at least partially overlaps a projection of the first conductive part on the surface. Each light-emitting diode includes a binding electrode, and the binding electrode is electrically connected to the second conductive part. The first conductive part is made of metal; the second conductive part is made of a transparent conductive oxide. The binding electrode is made of metal. A eutectic material is formed between the second conductive part and the binding electrode.

Abstract: A light-emitting array substrate allowing a higher efficiency in the seating of numerous very small light source elements includes a substrate, an insulating layer on the substrate including positioning holes, and light-emitting elements. Each positioning hole penetrates the insulating layer and forms a first opening and a second opening. For each positioning hole, a size of the bottommost first opening is less than a size of the topmost second opening, and, from topmost to bottommost of the substrate, a projection of the second opening on the substrate more than covers a projection of the first opening on the substrate. A method of fabricating the substrate and a display panel using the substrate are further disclosed.

Abstract: A display panel of micro LEDs which provides a means of testing the installed micro LEDs for illumination qualities before final connections are made includes a transparent substrate, a plurality of electrode blocks on the transparent substrate, a plurality of conductive bonding blocks, and the micro LEDs. Each electrode block includes a slit allowing light to pass through. Each bonding block is on a surface of one electrode block away from the transparent substrate and is partially embedded in the slit of one corresponding electrode block. Each micro LED is fixed on one electrode block by a corresponding bonding block and is electrically connected with the electrode block. A method of manufacturing the display panel is further provided.

Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.

Abstract: A manufacturing method of a thin film transistor includes hard-baking and etching processes for a stop layer. Two through holes are exposed and developed in a photoresistor layer, in which a distance between the two through holes is substantially equal to the channel length of the thin film transistor. Further, the etching stop layer is dry-etched to obtain the thin film transistor having an expected channel length.

Abstract: A manufacturing method of a thin film transistor includes hard-baking and etching processes for a stop layer. Two through holes are exposed and developed in a photoresistor layer, in which a distance between the two through holes is substantially equal to the channel length of the thin film transistor. Further, the etching stop layer is dry-etched to obtain the thin film transistor having an expected channel length.

Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.

Abstract: This invention discloses a defect isolation method for thin-film solar cell having at least a defect therein. The thin-film solar cell comprises a substrate, a front electrode layer, an absorber layer and a back electrode layer stacked in such a sequence. The defect isolation method includes the steps of: detecting at least a defect formed in thin-film solar cell and acquiring the positions of the defects, and applying a laser light to scribe the outer circumference of the defects according to the positions of the defects so as to form at least an isolation groove having a closed-curve configuration.

Abstract: The present invention discloses a thin film solar cell module and a manufacturing method thereof. The thin film solar cell comprises, from bottom to top, a first substrate, a first electrode, an absorber layer, and a second electrode layer. A first current output region formed at the positive electrode of the thin film solar cell module. A first current output element is disposed in the first current output region, and the absorber layer further comprises at least a first gap which is disposed in the first current output region to increase the contact between the first electrode layer and the second electrode layer. The useless current, the resistance and the heat generated there are reduced. The heat generated there is also reduced.

Abstract: This invention discloses a defect isolation method for thin-film solar cell having at least a defect therein. The thin-film solar cell comprises a substrate, a front electrode layer, an absorber layer and a back electrode layer stacked in such a sequence. The defect isolation method includes the steps of: detecting at least a defect formed in thin-film solar cell and acquiring the positions of the defects, and applying a laser light to scribe the outer circumference of the defects according to the positions of the defects so as to form at least an isolation groove having a closed-curve configuration.

Abstract: This invention discloses a thin-film solar cell, provided with a plurality of unit cells, comprising a substrate, a front electrode layer, an absorber layer and a back electrode layer stacked in such a sequence. The thin-film solar cell further includes at least a defect formed at least in the back electrode layer, and the defect has at least an isolation groove of a closed curve formed around the defect.

Abstract: A method for forming a silicon oxide layer in the production of the polysilicon film transistor is disclosed. A plasma surface treatment is performed over a substrate after an amorphous silicon layer has been formed on the substrate by PECVD to transform a portion of the amorphous silicon layer into a superficial oxide layer.

Abstract: The present invention provides a method of forming a low temperature polysilicon thin film transistor (LTPS TFT). A polysilicon layer including a channel region is formed first. A first and a second plasma enhanced chemical vapor deposition processes are sequentially performed to form a composite gate insulating layer composed of a TEOS-based silicon oxide layer and a silicon nitride layer on the channel region. Finally a gate electrode and a source/drain of the low temperature polysilicon thin film transistor are formed.

Abstract: First, a substrate with a polysilicon film is provided. Then, a gate insulating layer and a gate are formed on the polysilicon film in sequence. An ion implantation process is performed to form a source and a drain around the gate. After that, a first plasma enhanced chemical vapor deposition (PECVD) process is performed to form a silicon nitride layer over the substrate and the gate. A second plasma enhanced chemical vapor deposition process is then performed to form a TEOS based silicon oxide layer on the silicon nitride layer. A photo-etching process follows to form a contact hole extending through to the source and drain respectively. Then, a conductive layer is filled into the contact holes and electrically connected to the source and drain.

Abstract: First, a substrate with a polysilicon film is provided. Then, a gate insulating layer and a gate are formed on the polysilicon film in sequence. An ion implantation process is performed to form a source and a drain around the gate. After that, a first plasma enhanced chemical vapor deposition (PECVD) process is performed to form a silicon nitride layer over the substrate and the gate. A second plasma enhanced chemical vapor deposition process is then performed to form a TEOS based silicon oxide layer on the silicon nitride layer. A photo-etching process follows to form a contact hole extending through to the source and drain respectively. Then, a conductive layer is filled into the contact holes and electrically connected to the source and drain.

Abstract: A method for improving uniformity of a film in a plasma enhanced chemical vapor deposition system in a deposition chamber includes the following steps before a deposition procedure. Firstly, a cleaning procedure is performed to remove particles adhered onto an internal wall of the deposition chamber. Then, a pre-deposition procedure is performed to isolate contaminants generated during the clearing procedure. Afterward, a specified gas is introduced into the deposition chamber so as to stabilize a condition inside the deposition chamber.

Abstract: A method for forming a silicon oxide layer in the production of the polysilicon film transistor is disclosed. A plasma surface treatment is performed over a substrate after an amorphous silicon layer has been formed on the substrate by PECVD to transform a portion of the amorphous silicon layer into a superficial oxide layer.

Abstract: The present invention provides a method of forming a low temperature polysilicon thin film transistor (LTPS TFT). A polysilicon layer including a channel region is formed first. A first and a second plasma enhanced chemical vapor deposition processes are sequentially performed to form a composite gate insulating layer composed of a TEOS-based silicon oxide layer and a silicon nitride layer on the channel region. Finally a gate electrode and a source/drain of the low temperature polysilicon thin film transistor are formed.