Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: In a method of coating a photo resist over a wafer, dispensing the photo resist from a nozzle over the wafer is started while rotating the wafer, and dispensing the photo resist is stopped while rotating the wafer. After starting and before stopping the dispensing the photo resist, a wafer rotation speed is changed at least 4 times. During dispensing, an arm holding the nozzle may move horizontally. A tip end of the nozzle may be located at a height of 2.5 mm to 3.5 mm from the wafer.

Abstract: A light-emitting device includes: a semiconductor stack, including a first semiconductor layer, an active region and a second semiconductor layer; a first contact electrode and a second contact electrode formed on the semiconductor stack, wherein the first contact electrode includes a first contact part formed on the first semiconductor layer and the second contact electrode includes a second contact part formed on the second semiconductor layer; an insulating stack formed on the semiconductor stack, including an opening on the second contact part; a first electrode pad and a second electrode pad formed on the insulating stack, wherein the second electrode pad filled in the opening and connecting the second contact part; wherein the second electrode pad includes an upper surface, and the upper surface includes a platform area and a depression area on the second contact part; wherein the platform area has a maximum height relative to other areas of the upper surface; wherein an area of a projection of the plat

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: A reference current/voltage generator includes a current mirror unit and a current-mode temperature compensation unit. The current mirror unit generates a first current, a first sum current and a second sum current flowing through first to third terminals thereof, and the first current, the first sum current and the second sum current are in a multiple relationship. The current-mode temperature compensation unit is electrically connected to the second and third terminals of the current mirror unit, and when a voltage on the second terminal is equal to a voltage on the third terminal, the first sum current is a sum of a current proportional to absolute temperature (PTAT) and a current complementary to absolute temperature (CTAT). The first terminal of the current mirror unit is an output terminal of the reference current/voltage generator and configured to output the first current as a reference current.

Abstract: A reference current/voltage generator includes a current mirror unit and a current-mode temperature compensation unit. The current mirror unit generates a first current, a first sum current and a second sum current flowing through first to third terminals thereof, and the first current, the first sum current and the second sum current are in a multiple relationship. The current-mode temperature compensation unit is electrically connected to the second and third terminals of the current mirror unit, and when a voltage on the second terminal is equal to a voltage on the third terminal, the first sum current is a sum of a current proportional to absolute temperature (PTAT) and a current complementary to absolute temperature (CTAT). The first terminal of the current mirror unit is an output terminal of the reference current/voltage generator and configured to output the first current as a reference current.

Abstract: A chemical synthesis method to fabricate boron carbide to obtain boron carbide fine powders includes the steps of: (A) formulating a precursor solution including a boron source, a liquid organic carbon source and a catalyst; (B) subjecting the precursor solution to a pyrolytic reaction in the presence of electromagnetic radiation to obtain a boron carbide precursor; and (C) subjecting the boron carbide precursor to a thermal energy treatment in the presence of thermal energy to obtain boron carbide fine powders.

Abstract: This invention is announcing a composition of flavonoid skeleton in the formula I or formula II compound, wherein each of the substituents is given the definition as set forth in the specification and claims. This composition has the capacity to treating or preventing a virus infection in a subject.

Abstract: A chemical synthesis method to fabricate boron carbide to obtain boron carbide fine powders includes the steps of: (A) formulating a precursor solution including a boron source, a liquid organic carbon source and a catalyst; (B) subjecting the precursor solution to a pyrolytic reaction in the presence of electromagnetic radiation to obtain a boron carbide precursor; and (C) subjecting the boron carbide precursor to a thermal energy treatment in the presence of thermal energy to obtain boron carbide fine powders.

Abstract: This invention is announcing a composition of flavonoid skeleton in the formula I or formula II compound, wherein each of the substituents is given the definition as set forth in the specification and claims. This composition has the capacity to treating or preventing a virus infection in a subject.

Abstract: This invention is announcing a composition of flavonoid skeleton in the formula I or formula II compound, wherein each of the substituents is given the definition as set forth in the specification and claims. This composition have the capacity to treating or preventing a virus infection in a subject.

Abstract: This invention is announcing a composition of flavonoid skeleton in the formula I or formula II compound, wherein each of the substituents is given the definition as set forth in the specification and claims. This composition have the capacity to treating or preventing a virus infection in a subject.

Abstract: This invention is announcing a composition of flavonoid skeleton in the formula I or formula II compound, wherein each of the substituents is given the definition as set forth in the specification and claims. This composition have the capacity to treating or preventing a virus infection in a subject.

Abstract: A signal transmitter with adjustable signal power includes a housing, a first adjustable metal shielding layer and a circuit board. The first adjustable metal shielding layer is disposed within the housing. The area of the first adjustable metal shielding layer consists of a first shielding area and a first un-shielding area. The first shielding area and the first un-shielding area are adjustable. The circuit board is disposed within the housing, and is located below the first adjustable metal shielding layer. The circuit board is electrically connected with the first adjustable metal shielding layer, and includes a signal emission chip. The signal emission chip is configured for adjusting signal emission power to emit a signal according to the first un-shielding area of the first adjustable metal shielding layer. A message generating system and a signal power adjusting method are disclosed herein as well.