Patents by Inventor Hui-Chung BYUN

Hui-Chung BYUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11314590
    Abstract: A memory device includes a plurality of memory chips storing and outputting data in response to a control command and an address command, at least one ECC memory chip providing an error check and correction (ECC) function on the data stored and output by the plurality of the memory chips, and a controller, marking a memory chip in which a defective memory cell is detected among the plurality of memory chips, as a defective memory chip, storing data of the defective memory chip in the ECC memory chip, and controlling the defective memory chip to execute a post package repair (PPR).
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: April 26, 2022
    Inventors: Hui Chung Byun, Yoen Hwa Lee, Seung Hun Lee
  • Patent number: 11157342
    Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: October 26, 2021
    Inventors: Wonjae Shin, Tae-Kyeong Ko, Dae-Jeong Kim, Sung-Joon Kim, Wooseop Kim, Chanik Park, Yongjun Yu, Insu Choi, Hui-Chung Byun, JongYoung Lee
  • Publication number: 20200349000
    Abstract: A memory device includes a plurality of memory chips storing and outputting data in response to a control command and an address command, at least one ECC memory chip providing an error check and correction (ECC) function on the data stored and output by the plurality of the memory chips, and a controller, marking a memory chip in which a defective memory cell is detected among the plurality of memory chips, as a defective memory chip, storing data of the defective memory chip in the ECC memory chip, and controlling the defective memory chip to execute a post package repair (PPR).
    Type: Application
    Filed: July 21, 2020
    Publication date: November 5, 2020
    Inventors: Hui Chung BYUN, Yoen Hwa LEE, Seung Hun LEE
  • Patent number: 10754724
    Abstract: A memory device includes a plurality of memory chips storing and outputting data in response to a control command and an address command, at least one ECC memory chip providing an error check and correction (ECC) function on the data stored and output by the plurality of the memory chips, and a controller, marking a memory chip in which a defective memory cell is detected among the plurality of memory chips, as a defective memory chip, storing data of the defective memory chip in the ECC memory chip, and controlling the defective memory chip to execute a post package repair (PPR).
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui Chung Byun, Yoen Hwa Lee, Seung Hun Lee
  • Publication number: 20190310905
    Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.
    Type: Application
    Filed: October 18, 2018
    Publication date: October 10, 2019
    Inventors: Wonjae Shin, Tae-Kyeong KO, Dae-Jeong KIM, Sung-Joon KIM, Wooseop KIM, Chanik PARK, Yongjun YU, lnsu CHOI, Hui-Chung BYUN, JongYoung LEE
  • Publication number: 20190258538
    Abstract: A memory device includes a plurality of memory chips storing and outputting data in response to a control command and an address command, at least one ECC memory chip providing an error check and correction (ECC) function on the data stored and output by the plurality of the memory chips, and a controller, marking a memory chip in which a defective memory cell is detected among the plurality of memory chips, as a defective memory chip, storing data of the defective memory chip in the ECC memory chip, and controlling the defective memory chip to execute a post package repair (PPR).
    Type: Application
    Filed: September 5, 2018
    Publication date: August 22, 2019
    Inventors: Hui Chung BYUN, Yoen Hwa Lee, Seung Hun Lee
  • Publication number: 20190034270
    Abstract: A memory module including a plurality of memory chips each including DQ contact points which are grouped into at least one DQ group corresponding to a correction data width, a serial presence detect (SPD) chip configured to store DQ grouping information about the plurality of memory chips, and additional DQS contact points connected to the at least one DQ group, the additional DQS contact points configured to transmit signals to perform a data correction algorithm based on the correction data width in an error correction mode may be provided.
    Type: Application
    Filed: February 6, 2018
    Publication date: January 31, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hui-chung BYUN, Seung-hun LEE, Sun-woo LEE
  • Patent number: 10152114
    Abstract: A memory module includes a counter configured to count a number of commands received from a host to generate a counted number and provide the counted value to the host, a memory device configured to receive an operating frequency and an operating voltage from that host that are determined based on the counted number, and a serial presence detect (SPD) configured to store the operating frequency and operating voltage.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hui-Chung Byun
  • Publication number: 20170115915
    Abstract: A memory module includes a counter configured to count a number of commands received from a host to generate a counted number and provide the counted value to the host, a memory device configured to receive an operating frequency and an operating voltage from that host that are determined based on the counted number, and a serial presence detect (SPD) configured to store the operating frequency and operating voltage.
    Type: Application
    Filed: July 29, 2016
    Publication date: April 27, 2017
    Inventor: HUI-CHUNG BYUN
  • Publication number: 20110001467
    Abstract: A method of optimizing a driving voltage of an electronic device includes; iteratively varying the level of a driving voltage provided to the electronic device and performing an operation of the electronic device with each iteration until the operation fails, and then selecting as an operating level for the driving voltage, a level of the driving voltage for an iteration just prior to an iteration in which the operation fails.
    Type: Application
    Filed: June 1, 2010
    Publication date: January 6, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung Chan CHOI, Hee Joo CHOI, Seung Man SHIN, Hui-Chung BYUN