Patents by Inventor Hui Dong Lee
Hui Dong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10033562Abstract: An envelope signal time delay adjustment apparatus includes a negative group delay unit for converting an envelope signal input from a signal generator into an envelope signal having a group delay of a negative value whose frequency increases from a predetermined frequency band; an envelope-tracking modulator for power-amplifying and outputting the envelope signal output from the negative group delay unit; and a frequency limiting unit for limiting a bandwidth of the envelope-tracking modulator to be lower than an original bandwidth of the envelope-tracking modulator.Type: GrantFiled: March 16, 2017Date of Patent: July 24, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seung Hyun Jang, Bong Hyuk Park, Hui Dong Lee
-
Publication number: 20180205582Abstract: A data modulation apparatus may comprise a S2D conversion part including a first amplifier operating based on a carrier wave signal and two transformers receiving an output signal of the first amplifier; a first switch part transferring status of input data to the first amplifier based on the input data; a differential amplification part receiving output signals of the S2D conversion part and amplifying the output signals of the S2D conversion part; a D2S conversion part receiving output signals of the differential amplification part and performing modulation on the output signals by converting the output signals to a single signal; and a second switch part transferring the output signals of the differential amplification part to the D2S conversion part based on the input data. Here, the first switch part and the second switch part may be alternately turned on and off.Type: ApplicationFiled: January 12, 2018Publication date: July 19, 2018Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sun Woo KONG, Bong Hyuk PARK, Moon Sik LEE, Hui Dong LEE
-
Publication number: 20180167048Abstract: A matching circuit in a communication apparatus may comprise a first inductor disposed at a primary side of a transformer; a second inductor disposed at a secondary side of the transformer; and an impedance element connected to the first inductor and the second inductor. Also, a first terminal of the first inductor may be connected to an input terminal of the transformer, a second terminal of the first inductor may be connected to a common node connected to a ground, a first terminal of the second inductor may be connected to an output terminal of the transformer, a second terminal of the second inductor may be connected to the common node, a first terminal of the impedance element may be connected to the common node, and a second terminal of the impedance element may be connected to the ground.Type: ApplicationFiled: December 7, 2017Publication date: June 14, 2018Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sun Woo KONG, Cheol Ho KIM, Bong Hyuk PARK, Hui Dong LEE
-
Publication number: 20170302234Abstract: A high frequency amplifier circuit includes a transistor including a drain, a gate, and a source, an inductance-capacitor (LC) tank connected to the drain, and a transformer connected to the gate and the source.Type: ApplicationFiled: April 14, 2017Publication date: October 19, 2017Inventors: Sunwoo KONG, Bong Hyuk PARK, Moon-Sik LEE, Hui Dong LEE
-
Publication number: 20170272290Abstract: An envelope signal time delay adjustment apparatus includes a negative group delay unit for converting an envelope signal input from a signal generator into an envelope signal having a group delay of a negative value whose frequency increases from a predetermined frequency band; an envelope-tracking modulator for power-amplifying and outputting the envelope signal output from the negative group delay unit; and a frequency limiting unit for limiting a bandwidth of the envelope-tracking modulator to be lower than an original bandwidth of the envelope-tracking modulator.Type: ApplicationFiled: March 16, 2017Publication date: September 21, 2017Inventors: Seung Hyun JANG, Bong Hyuk PARK, Hui Dong LEE
-
Patent number: 9595980Abstract: Provided is an oscillation circuit including a voltage adjuster adjusting a magnitude of a power supply voltage according to a digital signal, an LC tank circuit connected between first and second nodes and generating a resonance signal on a basis of the magnitude adjusted power supply voltage, and a differential amplification circuit oscillating the resonance signal or modifying an oscillation state of the resonance signal to output first and second output voltage signals to the first and second nodes, respectively.Type: GrantFiled: April 7, 2015Date of Patent: March 14, 2017Assignee: Electronics and Telecommunications Research InstituteInventors: Hui Dong Lee, Bong Hyuk Park, Moon-Sik Lee
-
Patent number: 9490734Abstract: A motor control device including a preprocessing portion calculating a counter electromotive force using an analog operation is provided. The motor control device may include an offset compensation portion and a counter electromotive force measuring portion. The offset compensation portion receives a three-phase current signal from the motor and compensates an offset of the three-phase current signal. The counter electromotive force measuring portion receives the compensated current signal and a three-phase voltage signal from the motor and calculates the received current signal and the received voltage signal using an analog operation to provide the calculated result.Type: GrantFiled: April 10, 2012Date of Patent: November 8, 2016Assignee: ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jaewon Nam, Young Kyun Cho, Hui Dong Lee, Yil Suk Yang, Jong-Kee Kwon, Jongdae Kim
-
Publication number: 20160112075Abstract: Provided is an oscillation circuit including a voltage adjuster adjusting a magnitude of a power supply voltage according to a digital signal, an LC tank circuit connected between first and second nodes and generating a resonance signal on a basis of the magnitude adjusted power supply voltage, and a differential amplification circuit oscillating the resonance signal or modifying an oscillation state of the resonance signal to output first and second output voltage signals to the first and second nodes, respectively.Type: ApplicationFiled: April 7, 2015Publication date: April 21, 2016Applicant: Electronics and Telecommunications Research InstituteInventors: Hui Dong LEE, Bong Hyuk PARK, Moon-Sik LEE
-
Patent number: 9274151Abstract: A frequency comparator outputs an input reference signal and a comparison target signal as pulse-form signals, and is charged or discharged with a voltage corresponding to the reference signal to output a reference voltage having a variable first frequency range, and charged or discharged with a voltage corresponding to the comparison target signal to output a comparison target voltage having a variable second frequency range. The frequency comparator compares the reference voltage having the first frequency range and the comparison output voltage having the second frequency range.Type: GrantFiled: November 28, 2012Date of Patent: March 1, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hui Dong Lee, Jae Ho Jung
-
Patent number: 9106128Abstract: Provided is a charge pump circuit having a current mirror structure, including a first voltage controller including a plurality of first resistors and a plurality of first switches, and in response to a switching control signal corresponding to a bias current, driving the plurality of first switches to allow a current path passing through the plurality of first resistors to bypass, thereby controlling a voltage level of an output end, a second voltage controller including a plurality of second resistors and a plurality of second switches, and in response to the switching control signal, driving the plurality of second switches to allow a current path passing through the plurality of second resistors to bypass, thereby controlling a voltage level of an output end to correspond to the voltage of the output end of the first voltage controller.Type: GrantFiled: June 23, 2014Date of Patent: August 11, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Hui Dong Lee, Jae Ho Jung, Kwangchun Lee
-
Publication number: 20150200589Abstract: Provided is a charge pump circuit having a current mirror structure, including a first voltage controller including a plurality of first resistors and a plurality of first switches, and in response to a switching control signal corresponding to a bias current, driving the plurality of first switches to allow a current path passing through the plurality of first resistors to bypass, thereby controlling a voltage level of an output end, a second voltage controller including a plurality of second resistors and a plurality of second switches, and in response to the switching control signal, driving the plurality of second switches to allow a current path passing through the plurality of second resistors to bypass, thereby controlling a voltage level of an output end to correspond to the voltage of the output end of the first voltage controller.Type: ApplicationFiled: June 23, 2014Publication date: July 16, 2015Inventors: Hui Dong LEE, Jae Ho JUNG, Kwangchun LEE
-
Patent number: 9083360Abstract: A lock detector and a clock generator including the same are disclosed. A lock detector includes a counter unit which counts a non-matching section of a first signal and a second signal to provide a count value, the first signal and the second signal being comparison result signals obtained by comparing a phase of a reference signal with a phase of a comparison signal, and a lock detection unit which outputs a lock detection signal based on a result of comparing the count value with the reference value. Accordingly, a lock state of the phase-locked loop can be detected rapidly and exactly.Type: GrantFiled: September 25, 2013Date of Patent: July 14, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Hui Dong Lee, Kwang Chun Lee, Jae Ho Jung
-
Patent number: 8841951Abstract: Disclosed is an apparatus for controlling a duty ratio of a signal that includes a clock control unit configured to generate a plurality of control signals based on an input signal, a half-cycle generation unit configured to generate a multiplied signal by use of the input signal and a delay signal that is obtained by delaying the input signal based on a delay control voltage, and divide the multiplied signal to generate a first division signal and a second division signal that are in inverse relation to each other, a comparator unit configured to compare a pulse width of the first division signal with a pulse width of the second division signal based on the control signal provided by the clock control unit, and output a delay control signal corresponding to a result of the comparison, and a control voltage generation unit configured to output a delay control voltage.Type: GrantFiled: October 30, 2013Date of Patent: September 23, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Hui Dong Lee, Jae Ho Jung, Kwang Chun Lee
-
Patent number: 8836259Abstract: Provided is a sensorless BLDC motor system. The sensorless BLDC motor system includes a BLDC motor, a comparator, a motor controller, a three-phase inverter, and a mode selector. The BLDC motor includes first to third coils. The comparator compares a voltage of a specific coil of the first to third coils with a neutral-point voltage to output the compared result. The voltage of the specific coil becomes equal to the neutral-point voltage and a specific time elapses, and then the motor controller generates first and second coil control signals based on the compared result. The three-phase inverter supplies a source voltage or ground voltage to the specific coil, or floats the specific coil, in response to the first and second coil control signals. The mode selector selects a driving mode of the BLDC motor by adjusting the specific time.Type: GrantFiled: January 10, 2012Date of Patent: September 16, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Young Kyun Cho, Hui Dong Lee, Jaewon Nam, Jong-Kee Kwon
-
Publication number: 20140118045Abstract: Disclosed is an apparatus for controlling a duty ratio of a signal that includes a clock control unit configured to generate a plurality of control signals based on an input signal, a half-cycle generation unit configured to generate a multiplied signal by use of the input signal and a delay signal that is obtained by delaying the input signal based on a delay control voltage, and divide the multiplied signal to generate a first division signal and a second division signal that are in inverse relation to each other, a comparator unit configured to compare a pulse width of the first division signal with a pulse width of the second division signal based on the control signal provided by the clock control unit, and output a delay control signal corresponding to a result of the comparison, and a control voltage generation unit configured to output a delay control voltage.Type: ApplicationFiled: October 30, 2013Publication date: May 1, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Hui Dong LEE, Jae Ho JUNG, Kwang Chun LEE
-
Publication number: 20140085016Abstract: A lock detector and a clock generator including the same are disclosed. A lock detector includes a counter unit which counts a non-matching section of a first signal and a second signal to provide a count value, the first signal and the second signal being comparison result signals obtained by comparing a phase of a reference signal with a phase of a comparison signal, and a lock detection unit which outputs a lock detection signal based on a result of comparing the count value with the reference value. Accordingly, a lock state of the phase-locked loop can be detected rapidly and exactly.Type: ApplicationFiled: September 25, 2013Publication date: March 27, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Hui Dong LEE, Kwang Chun LEE, Jae Ho JUNG
-
Patent number: 8604845Abstract: Disclosed is a triangular wave generator which includes a square wave signal generating unit configured to output a first signal transitioning to a high level from a low level via an output terminal in response to a first transition of a clock signal and to transition the first signal to a low level from a high level in response to a reset signal; a resistance unit configured to adjust a voltage level of a the square wave signal; and a capacitance unit configured to receive an output signal of the resistance unit to generate a second signal rising to a high level from a low level with a slope, to provide the reset signal to the square wave signal generating unit, and to output a triangular signal by falling the second signal to a low level from a high level with a slope.Type: GrantFiled: June 4, 2012Date of Patent: December 10, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Hui Dong Lee, Jaewon Nam, Young Kyun Cho, Jong-Kee Kwon, Yil Suk Yang, Jongdae Kim
-
Patent number: 8446194Abstract: Provided is a spread spectrum clock generating circuit. The spread spectrum clock generating circuit includes: a phase detector receiving a reference frequency signal from the external and detecting a phase difference between the reference frequency signal and a frequency-divided signal; a voltage controlled oscillator outputting an oscillation signal corresponding to a detection result of the phase detector; a main divider generating the frequency-divided signal by dividing a frequency of the oscillation signal by a main dividing ratio; and a dividing ratio controller generating a variable count value, generating a sub dividing ratio by performing delta-sigma modulation according to the count value, and adjusting the main dividing ratio according to the sub dividing ratio.Type: GrantFiled: October 18, 2011Date of Patent: May 21, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Seok Ju Yun, Hui Dong Lee, Kwi Dong Kim, Jong-Kee Kwon
-
Publication number: 20130027094Abstract: Disclosed is a triangular wave generator which includes a square wave signal generating unit configured to output a first signal transitioning to a high level from a low level via an output terminal in response to a first transition of a clock signal and to transition the first signal to a low level from a high level in response to a reset signal; a resistance unit configured to adjust a voltage level of a the square wave signal; and a capacitance unit configured to receive an output signal of the resistance unit to generate a second signal rising to a high level from a low level with a slope, to provide the reset signal to the square wave signal generating unit, and to output a triangular signal by falling the second signal to a low level from a high level with a slope.Type: ApplicationFiled: June 4, 2012Publication date: January 31, 2013Applicant: Electronics and Telecommunications Research InstituteInventors: Hui Dong LEE, Jaewon Nam, Young Kyun Cho, Jong-Kee Kwon, Yil Suk Yang, Jongdae Kim
-
Phase locked loop circuit including automatic frequency control circuit and operating method thereof
Patent number: 8350608Abstract: Provided is a PLL circuit including automatic frequency control circuit and an operating method thereof. The voltage controlled oscillator is primarily controlled by an automatic frequency control circuit, and is secondarily controlled by a loop filter. The voltage controlled oscillator outputs a coarsely-tuned oscillation signal when primarily controlled, and outputs a finely-tuned oscillation signal when secondarily controlled. The PLL circuit can have a quick frequency fixing time, and output the oscillation signal having a broad and stable frequency. Moreover, the noise characteristic of the PLL circuit is enhanced.Type: GrantFiled: December 22, 2010Date of Patent: January 8, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Hui Dong Lee, Seok Ju Yun, Kwi Dong Kim, Jong-Kee Kwon, Sang-Hyun Cho