Abstract: The structure and method of measuring the capacitance comprising a first buried doped area and a heavily doped area in a semiconductor substrate. The heavily doped area is parallel to the buried doped area. Several second buried doped areas, the first oxide layers and the second oxide layers are formed in the semiconductor substrate. Any of the second buried doped areas is perpendicular to the first buried doped area. One end of the second buried doped area is connected to the first buried doped area, and another end is connected to the heavily doped area. Any of the first oxide layers is overlaid on the second buried doped area. Any of the second oxide layers is placed between any two first oxide layers, and the thickness of the second oxide layer is thinner than the thickness of the first oxide layer. At least two first and several second polysilicon rows are formed on the semiconductor substrate, and wherein two first polysilicon rows are respectively placed on two sides of the second buried doped areas.