Patents by Inventor Hui-Hsien Wu
Hui-Hsien Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968840Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.Type: GrantFiled: November 10, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
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Publication number: 20240126861Abstract: A device unlocking method and an electronic device are provided. The method includes: detecting fingerprint information of a user by a first sensor of the electronic device; authenticating the fingerprint information and temporarily storing an authentication result of the fingerprint information; after authenticating the fingerprint information, detecting operation environment information related to the electronic device by a second sensor of the electronic device; and in response to the operation environment information meeting a default condition, unlocking the electronic device according to the authentication result.Type: ApplicationFiled: May 9, 2023Publication date: April 18, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Chih-Hsien Yang, Hui-Fen Chen, I-Hsi Wu
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Patent number: 11942563Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.Type: GrantFiled: June 1, 2023Date of Patent: March 26, 2024Assignee: XINTEC INC.Inventors: Chia-Sheng Lin, Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen
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Publication number: 20240096706Abstract: The present disclosure provides a method of forming a semiconductor device. The method includes: forming an interconnect structure over a substrate; forming a first gate structure and a second gate structure in a first layer of the interconnect structure; forming a first metal oxide layer and a second metal oxide layer in a second layer of the interconnect structure over the first gate structure and the second gate structure, respectively; forming an implant mask over the first metal oxide layer and the second metal oxide layer, the implant mask having different thicknesses corresponding to the first metal oxide layer and the second oxide layer; and performing an implantation operation on the first metal oxide layer and the second metal oxide layer.Type: ApplicationFiled: January 12, 2023Publication date: March 21, 2024Inventors: YEN-CHUNG HO, YONG-JIE WU, HUI-HSIEN WEI
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Patent number: 11705368Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.Type: GrantFiled: July 13, 2021Date of Patent: July 18, 2023Assignee: XINTEC INC.Inventors: Chia-Sheng Lin, Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen
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Publication number: 20210343591Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.Type: ApplicationFiled: July 13, 2021Publication date: November 4, 2021Inventors: Chia-Sheng Lin, Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen
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Patent number: 11137559Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.Type: GrantFiled: April 17, 2020Date of Patent: October 5, 2021Assignee: XINTEC INC.Inventors: Jiun-Yen Lai, Yu-Ting Huang, Hsing-Lung Shen, Tsang-Yu Liu, Hui-Hsien Wu
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Patent number: 11121031Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.Type: GrantFiled: October 30, 2019Date of Patent: September 14, 2021Assignee: XINTEC INC.Inventors: Chia-Sheng Lin, Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen
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Publication number: 20200333542Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.Type: ApplicationFiled: April 17, 2020Publication date: October 22, 2020Inventors: Jiun-Yen LAI, Yu-Ting HUANG, Hsing-Lung SHEN, Tsang-Yu LIU, Hui-Hsien WU
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Publication number: 20200144116Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.Type: ApplicationFiled: October 30, 2019Publication date: May 7, 2020Inventors: Chia-Sheng LIN, Hui-Hsien WU, Jian-Hong CHEN, Tsang-Yu LIU, Kuei-Wei CHEN
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Patent number: 9947716Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.Type: GrantFiled: November 22, 2016Date of Patent: April 17, 2018Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Hsiao-Lan Yeh, Chia-Sheng Lin, Yi-Ming Chang, Po-Han Lee, Hui-Hsien Wu, Jyun-Liang Wu, Shu-Ming Chang, Yu-Lung Huang, Chien-Min Lin
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Patent number: 9875912Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.Type: GrantFiled: November 21, 2016Date of Patent: January 23, 2018Assignee: XINTEC INC.Inventors: Yen-Shih Ho, Hsiao-Lan Yeh, Chia-Sheng Lin, Yi-Ming Chang, Po-Han Lee, Hui-Hsien Wu, Jyun-Liang Wu
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Publication number: 20170148844Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.Type: ApplicationFiled: November 22, 2016Publication date: May 25, 2017Inventors: Yen-Shih HO, Hsiao-Lan YEH, Chia-Sheng LIN, Yi-Ming CHANG, Po-Han LEE, Hui-Hsien WU, Jyun-Liang WU, Shu-Ming CHANG, Yu-Lung HUANG, Chien-Min LIN
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Publication number: 20170148694Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.Type: ApplicationFiled: November 21, 2016Publication date: May 25, 2017Inventors: Yen-Shih HO, Hsiao-Lan YEH, Chia-Sheng LIN, Yi-Ming CHANG, Po-Han LEE, Hui-Hsien WU, Jyun-Liang WU
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Publication number: 20130300947Abstract: The present invention provides a mini-projector applied for a video output device. The video output device includes a microprocessor. A projection optical engine is coupled to the microprocessor for projecting a video data. A charging module is capable of charging to a first battery of the mini-projector and/or a second battery of the video output device. A male connector is couple to a female connector of the video output device. A switching unit is coupled to the charging module for switching the projecting function of the projection optical engine or the charging function of the second battery of the video output device.Type: ApplicationFiled: May 9, 2012Publication date: November 14, 2013Inventors: Hui Hsien Wu, Wei Hong Chen, Heng Liu, Cheng Tien Chen
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Publication number: 20130169887Abstract: The present invention provides a projection application device which is working through a wireless video output device and its video output control unit. The video output device includes a microprocessor. A video output unit is coupled to the microprocessor for outputting a video data. A video output control unit is coupled to the microprocessor for controlling a projecting image outputted by the projection device. The video output control unit includes a designation unit for designating the video data to the projection device or the video output device.Type: ApplicationFiled: January 3, 2012Publication date: July 4, 2013Applicant: AIPTEK INTERNATIONAL INC.Inventors: Hui-Hsien WU, Wei-Hong CHEN, Heng LIU
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Patent number: D679311Type: GrantFiled: January 3, 2012Date of Patent: April 2, 2013Assignee: Aiptek International Inc.Inventors: Hui-Hsien Wu, Wei-Hong Chen, Heng Liu