Patents by Inventor Hui Hsu

Hui Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240353502
    Abstract: This document describes systems and techniques directed at a machine-learning-based greedy optimization mechanism for reducing radio-frequency (RF) tests in production. In aspects, a process capability index is disclosed, the process capability index used to refine a test-set. The test-set includes tests configured to be performed on an electronic device. The process capability index is configured based on upper specification limits and lower specification limits of the electronic device for each test in the test-set, as well as results for each of the tests in the test-set. The process capability index is further configured based on a new upper specification limit and a new lower specification limit of the electronic device for a new test not in the test-set, as well as results for the new test.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicant: Google LLC
    Inventors: Xianren Wu, Ying Luo, Daniel Minare Ho, Chung-Cheng Tseng, Wenxiao Wang, Daniel Khuong, Ren-Hua Chang, Chen-Chun Hsiao, Chien An Hsu, Hui Peng, Song Liu, Yujing Li
  • Patent number: 12125948
    Abstract: A semiconductor device includes a semiconductor layered structure, an electrode unit, and an anti-adsorption layer. The electrode unit is disposed on an electrode connecting region of the semiconductor layered structure, and is a multi-layered structure. The anti-adsorption layer is disposed on a top surface of the electrode unit opposite to the semiconductor layered structure. Also disclosed herein is a light-emitting system including the semiconductor device.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: October 22, 2024
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Gong Chen, Chuan-gui Liu, Ting-yu Chen, Su-hui Lin, Ling-yuan Hong, Sheng-hsien Hsu, Kang-wei Peng, Chia-hung Chang
  • Patent number: 12119053
    Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: October 15, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen-Yang Hsueh, Ling-Hsiu Chou, Chih-Yang Hsu
  • Publication number: 20240337951
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Cheng CHEN, Chia-Jen CHEN, Hsin-Chang LEE, Shih-Ming CHANG, Tran-Hui SHEN, Yen-Cheng HO, Chen-Shao HSU
  • Publication number: 20240339427
    Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 10, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Kuo-Lung Pan, Sen-Kuei Hsu, Tin-Hao Kuo, Yi-Yang Lei, Ying-Cheng Tseng, Chi-Hui Lai
  • Publication number: 20240313642
    Abstract: A power factor correction circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first inductance coil, a second inductance coil, a first capacitor, and a second capacitor. The first switch is connected to the second switch, the third switch, and the first inductance coil. The fifth switch is connected to the third switch and the second inductance coil. The sixth switch is connected to the first switch, the fourth switch, and the seventh switch. The seventh switch is further connected to the second switch, the first capacitor, and the second capacitor. The second inductance coil is further connected to the fourth switch and the first capacitor. The second capacitor is connected to the fourth switch, the sixth switch, and the first switch.
    Type: Application
    Filed: June 13, 2023
    Publication date: September 19, 2024
    Inventors: TE-HUNG YU, YU-CHENG LIN, MIN-HAO HSU, CHIA-HUI LIANG
  • Patent number: 12088020
    Abstract: An antenna structure is applicable in an electronic device having a metal frame. At least one slot is defined in the metal frame. The antenna structure includes a first radiating portion, a second radiating portion, and an antenna module. The first radiating portion and the second radiating portion are portions of the metal frame. The second radiating portion is separated from the first radiating portion with the at least one slot. The antenna module is spaced from an inner side of the metal frame. A projection of the antenna module is partially overlapping a projection of the first radiating portion or a projection of the second radiating portion in a predetermined direction, the antenna structure excites a plurality of radiation modes. The application also provides an electronic device with the antenna structure.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: September 10, 2024
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Cho-Kang Hsu, Min-Hui Ho
  • Patent number: 12087885
    Abstract: Disclosed is a light-emitting diode which includes a light-emitting epitaxial layered unit, an insulation layer, a transparent conductive layer, a protective layer, a first electrode, and a second electrode. The light-emitting epitaxial layered unit includes a first semiconductor layer, a second semiconductor layer, and a light-emitting layer sandwiched between the first and second semiconductor layers, and has a first electrode region which includes a pad area and an extension area. The insulation layer is disposed on the first semiconductor layer and at the extension area of the first electrode region. Also disclosed is a method for manufacturing the light-emitting diode.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: September 10, 2024
    Assignee: Quanzhou San'an Semiconductor Technology Co., Ltd.
    Inventors: Su-hui Lin, Feng Wang, Ling-yuan Hong, Sheng-Hsien Hsu, Sihe Chen, Dazhong Chen, Kang-Wei Peng, Chia-Hung Chang
  • Publication number: 20240291210
    Abstract: A connector assembly includes a guiding shield cage, a light guide member and a light guide member assembling construction. The guiding shield cage includes a top wall, a side wall, a bottom wall, and a supporting plate which extends from the bottom wall and is positioned at an outer side of the side wall. The light guide member is provided at the outer side of the side wall of the guiding shield cage and is upwardly supported by the supporting plate. The light guide member assembling construction includes a first latching construction and a second latching construction, the first latching construction is provided between the light guide member and the supporting plate which extends from the bottom wall, the second latching construction is provided between the light guide member and the top wall.
    Type: Application
    Filed: February 16, 2024
    Publication date: August 29, 2024
    Inventors: Chao-Hung Hsu, Tsai-Hui Chien
  • Patent number: 12068527
    Abstract: An antenna structure with wide radiation bandwidth in a reduced physical space includes a housing, a first feed portion, and a second feed portion. The housing includes a metallic side frame, a metallic middle frame, and a metallic back board. The metallic side frame defines first and second gaps, and the metallic back board defines a slot. The slot, the first gap, and the second gap divide the metallic side frame to give a first radiation portion. The first and second feed portions are both electrically connected to the first radiation portion. When the first feed portion supplies a current, the current flows through the first radiation portion, toward the second gap to excite a first working mode. When the second feed portion supplies a current, the current flows through the first radiation portion, toward the first gap to excite a second working mode.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: August 20, 2024
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Cho-Kang Hsu, Min-Hui Ho, Te-Chang Lin
  • Patent number: 12068529
    Abstract: An electronic device includes a metal frame, a middle frame, and at least one antenna feed module. The metal frame includes an upper metal frame, a first side metal frame, a bottom metal frame, and a second side metal frame sequentially connected. The middle frame, spaced apart from the first side metal frame and the second side metal frame, forms a slit, the at least one antenna feed module is received in the slit.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: August 20, 2024
    Assignee: FIH CO., LTD.
    Inventors: Cho-Kang Hsu, Min-Hui Ho, Yen-Hui Lin, Wei-Cheng Su
  • Patent number: 12062856
    Abstract: An antenna coupled feed module is received in a slit formed between a metal frame and at least one electronic component of an electronic device. The antenna coupled feed module includes a substrate, at least one coupled feed portion, an active circuit, a metal layer, and a non-conductive layer. The coupled feed portion and the active circuit are disposed on opposite surfaces of the substrate; the coupled feed portion couples the electrical signals to the metal layer, the metal layer conducts the electrical signals to the metal frame to radiate wireless signals; the non-conductive layer is arranged between the metal layer and the at least one coupled feed portion, and covers the coupled feed portion; the active circuit switches the electrical signals fed to the coupled feed portion. An electronic device with the antenna coupled feed module is also provided.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: August 13, 2024
    Assignee: FIH CO., LTD.
    Inventors: Cho-Kang Hsu, Min-Hui Ho
  • Patent number: 12051666
    Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Kuo-Lung Pan, Sen-Kuei Hsu, Tin-Hao Kuo, Yi-Yang Lei, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 12051896
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su, Chia-Wei Hsu, Ming-Fu Tsai, Shu-Yu Su, Li-Wei Chu, Jam-Wem Lee, Chia-Jung Chang, Hsiang-Hui Cheng
  • Patent number: 12038693
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Cheng Chen, Chia-Jen Chen, Hsin-Chang Lee, Shih-Ming Chang, Tran-Hui Shen, Yen-Cheng Ho, Chen-Shao Hsu
  • Publication number: 20240215457
    Abstract: Methods for fabricating a magnetoresistive random access memory are disclosed. In this method, an MTJ stack is formed over a lower metal layer on a semiconductor substrate, and a first etching is then performed to form an MTJ component and to expose a portion of a bottom electrode layer or via beneath the MTJ stack. An oxidation process is then carried out to oxidize both a conductive redeposition on sidewalls of the MTJ component and a partial thickness of the exposed portion of the bottom electrode layer or via around the MTJ component. Subsequently, a second etching is conducted at an incident etching angle of smaller than 45°, which facilitates complete removal of the resulting sidewall oxide layer on the MTJ component, as well as damaged portions thereof which may degrade the performance of the MTJ component, ensuring reliability of the MTJ component.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Inventors: Wei-Chuan CHEN, Hong-Hui HSU, Chih-Yuan LEE, Yiheng XU
  • Patent number: 11978510
    Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: May 7, 2024
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Yi Jiang, Kai Kang, Juan Boon Tan
  • Patent number: 11955794
    Abstract: A surge protection system includes a receptacle body, at least one power output jack, a power obtaining device, at least one surge protection module, a microcontroller unit, and a surge detection circuit. The at least one surge protection module includes a housing, a memory element, and a surge protection circuit that includes a surge absorption element and a thermal fuse connected in series and parallel. The surge absorption element absorbs a surge inputted from an external power supply, and the memory element records a number of surges carried by the surge absorption element. When the surge enters the surge protection system from the external power supply, the surge absorption element absorbs the surge, and the surge detection circuit outputs a signal to the microcontroller unit that writes the number of surges carried by the surge absorption element into the memory element.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: April 9, 2024
    Assignee: POWERTECH INDUSTRIAL CO., LTD.
    Inventors: Jung-Hui Hsu, Po-Hua Hsu, Chi-Chien Chen
  • Patent number: 11942375
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsing-Hui Hsu, Po-Nien Chen, Yi-Hsuan Chung, Bo-Shiuan Shie, Chih-Yung Lin
  • Publication number: 20240097388
    Abstract: An extension socket capable of rotation and a ground-electrode conductive structure thereof are provided. The ground-electrode conductive structure includes at least two ground-electrode conductive units. Each of the at least two ground-electrode conductive units has a ground-electrode clamping portion and a ground-electrode connecting portion formed by extending from an end of the ground-electrode clamping portion. A ground-electrode pivot portion is disposed at an end of each of the ground-electrode connecting portions away from the ground-electrode clamping portion. The at least two ground-electrode conductive units are pivotally connected with each other through the ground-electrode pivot portions of two adjacent ones of the ground-electrode connecting portions.
    Type: Application
    Filed: June 16, 2023
    Publication date: March 21, 2024
    Inventor: JUNG-HUI HSU