Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Abstract: A power supply circuit is provided. The power factor correction (PFC) circuit is used to perform a power factor correction according to a first voltage to generate an intermediate voltage. The first storage capacitor is used to store a first electrical energy related to the intermediate voltage. The boost conversion circuit is connected to the PFC circuit and used to generate an output voltage according to the intermediate voltage. The boost conversion circuit includes a first post-stage inductor, a first post-stage diode and a first post-stage transistor. The second storage capacitor is used to store a second electrical energy related to the output voltage. The capacitance value of the second storage capacitor is less than the capacitance value of the first storage capacitor; the first electrical energy is completely or partially transferred as the second electrical energy.

Abstract: An electronic device and a method for determining scenario data of a self-driving car are provided. The method includes: obtaining training scenario data by using scenario data, a loss function and a self-driving program module; training an encoding module and a decoding module by using the training scenario data, and generating a scenario space by using the trained encoding module; obtaining a monitoring module by using the scenario space; and executing the monitoring module to determine whether current scenario data belongs to an operational design domain by using the current scenario data and the trained encoding module.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.

Abstract: Methods and systems for thermal management of hardware resources that may be used to provide computer implemented services are disclosed. The disclosed thermal management method and systems may improve the likelihood of data processing systems providing desired computer implemented services by improving the thermal management of the hardware resources without impairment of storage devices. To improve the likelihood of the computer implemented services being provided, the systems may proactively identify whether storage devices subject to impairment due to dynamic motion are present. If such storage devices are present, then the system may automatically take action to reduce the likelihood of the storage devices being subject to dynamic motion sufficient to impair their operation.

Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.

Abstract: An antenna structure with multiple frequency capabilities applied to an electronic device includes frame body, first feed point, a first switch point, and second switch point. The frame body has at least one portion made of metal material and defines two gaps. The frame body between gaps form a first radiation portion. The first feed point from a source feeds current and signal to the first radiation portion. The first switch point and the second switch point are located at two ends of the frame body adjacent to the first gap. The first switch point and the second switch point are grounded through a switch circuit.

Abstract: A surge protection system includes a receptacle body, at least one power output jack, a power obtaining device, at least one surge protection module, a microcontroller unit, and a surge detection circuit. The at least one surge protection module includes a housing, a memory element, and a surge protection circuit that includes a surge absorption element and a thermal fuse connected in series and parallel. The surge absorption element absorbs a surge inputted from an external power supply, and the memory element records a number of surges carried by the surge absorption element. When the surge enters the surge protection system from the external power supply, the surge absorption element absorbs the surge, and the surge detection circuit outputs a signal to the microcontroller unit that writes the number of surges carried by the surge absorption element into the memory element.

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

Abstract: An extension socket capable of rotation and a ground-electrode conductive structure thereof are provided. The ground-electrode conductive structure includes at least two ground-electrode conductive units. Each of the at least two ground-electrode conductive units has a ground-electrode clamping portion and a ground-electrode connecting portion formed by extending from an end of the ground-electrode clamping portion. A ground-electrode pivot portion is disposed at an end of each of the ground-electrode connecting portions away from the ground-electrode clamping portion. The at least two ground-electrode conductive units are pivotally connected with each other through the ground-electrode pivot portions of two adjacent ones of the ground-electrode connecting portions.

Abstract: A bonded assembly includes an interposer; a semiconductor die that is attached to the interposer and including a planar horizontal bottom surface and a contoured sidewall; a high bandwidth memory (HBM) die that is attached to the interposer; and a dielectric material portion contacting the semiconductor die and the interposer. The contoured sidewall includes a vertical sidewall segment and a non-horizontal, non-vertical surface segment that is adjoined to a bottom edge of the vertical sidewall segment and is adjoined to an edge of the planar horizontal bottom surface of the semiconductor die. The vertical sidewall segment and the non-horizontal, non-vertical surface segment are in contact with the dielectric material portion. The contoured sidewall may provide a variable lateral spacing from the HBM die to reduce local stress in a portion of the HBM die that is proximal to the interposer.

Abstract: A wireless device is provided and includes a substrate, a first coil and a second coil. The first coil is configured to be wound around a first axis, and the first coil is disposed on the substrate and is configured to operate in a wireless charging mode. The second coil is disposed on the substrate and configured to operate in a wireless communication mode. The wires of the second coil partially overlap the wires of the first coil.

Abstract: An antenna structure applied in a wireless communication device includes a metal frame, a first feed portion, a second feed portion, and a ground portion. The metal frame defines a first gap and a second gap. A portion of the metal frame positioned between the first gap and the second gap forms the first radiation portion. The first feed portion is electrically connected to the first radiation portion and a first signal feed point for feeding current and signals to the first radiation portion. The second feed portion is positioned apart from the first feed portion, electrically connected to the first radiation portion and a second signal feed point for feeding current and signal to the first radiation portion. The ground portion is positioned between the first feed portion and the second feed portion and is connected to the first radiation portion for grounding the first radiation portion.

Abstract: The present disclosure provides a method of preparing mimicking angiogenic co-spheroids, including: co-cultring a neural related cell and a cultured cell on hyaluronan-grafted chitosan (CS-HA) substrates to form a co-spheroid of neural related cell/cultured cell, and encapsulating the co-spheroid of neural related cell/cultured cell into a hydrogel to form a mimicking angiogenic co-spheroid. The mimicking angiogenic co-spheroid of the present disclosure can be formed by 3D printing model as a 3D mini-neurovascular unit, which is applicated to a high-throughput angiogenesis screening platform.

Abstract: A laser processing system includes a laser source, an optical splitting unit, a frequency conversion unit and at least one optical mixer. The optical splitting unit is provided to divide light emitted by the laser source into a first light and a second light, and the first light and the second light have the same wavelength range. The frequency conversion unit is provided to convert the second light into a working light. The working light includes a frequency converted light, and the frequency converted light and the second light have different wavelength ranges. The optical mixer is provided to mix the first light with the frequency converted light.

Abstract: An optical engine module configured to receive an illuminating beam is provided. The illuminating beam includes a first illuminating beam with a first linear polarization state. The optical engine module includes a first polarization beam splitting element, a first phase retardation element, and a first light valve. The first polarization beam splitting element is disposed on the transmission path of the illuminating beam and is configured to reflect the first illuminating beam to the first phase retardation element. The first phase retardation element is disposed on the transmission path of the first illuminating beam, and the first illuminating beam passes through the first phase retardation element and is transmitted to the first light valve. The first light valve is disposed on the transmission path of the first illuminating beam and is configured to convert the first illuminating beam into a first image beam.

Abstract: The disclosed subject matter relates generally to resistive memory devices and methods of forming the same. More particularly, the present disclosure relates to two terminal and three terminal resistive random-access (ReRAM) memory devices with a cavity arranged between electrodes.

Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.