Abstract: The present disclosure describes a semiconductor device having fin structures with optimized fin pitches for substantially uniform S/D structures. The semiconductor device includes multiple fin structures on a substrate. The multiple fin structures have a first pitch and a second pitch in an alternate configuration and the second pitch is different from the first pitch. The semiconductor device further includes a gate structure on the multiple fin structures and a source/drain (S/D) structure adjacent to the gate structure and in contact with the multiple fin structures.

Abstract: Embodiments of the present disclosure provide a FinFET transistor having a gate structure including one or more non-conformal work function metal layers. In some embodiments, work function metal layers may be non-conformal in at least one of thickness, composition, and/or phases. The non-conformality in the work function metal layer lowers leakage, improve device performance, and increase device reliability.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according to one embodiment includes forming a plurality of fins protruding from a substrate, forming first and second dummy gate stacks over the fins, and depositing a cover structure over the fins. A first portion of the cover structure extends between the first and second dummy gate stacks. The method also includes etching the fins to form a first trench between the first dummy gate stack and the first portion of the cover structure and a second trench between the second dummy gate stack and the first portion of the cover structure, removing the cover structure, epitaxially growing a first epitaxial feature from the first trench and a second epitaxial feature from the second trench. The first and second epitaxial features merge after rising above a top surface of the fins.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes depositing a dummy gate material layer over a first fin-shaped active region, patterning the dummy gate material layer to form a dummy gate electrode, wherein the dummy gate electrode has a footing feature at an interface between the first fin-shaped active region and the dummy gate electrode, oxidizing the footing feature and a sidewall portion of the dummy gate electrode to form a dielectric gate spacer, and replacing a remaining portion of the dummy gate electrode with a gate structure.

Abstract: Embodiments of the present disclosure provide a FinFET semiconductor including a first set of fin structures that are active, a source/drain (S/D) region in contact with the first set of fin structures, a second set of fin structures separated, via a shallow trench isolation (STI) feature, from the first set of fin structures, a contact etch stop layer (CESL) over the S/D region and over the second set of fin structures, and a gate over the first set of fin structures and over the second set of fin structures, the gate including a gate dielectric and a gate electrode over the gate dielectric. The second set of fin structures includes one or more non-active fin structures that are in contact with the CESL without being in contact with the S/D region.

Abstract: A semiconductor structure includes a first circuit area having first fin active regions extending lengthwise along a first direction, each of the first fin active regions includes first channel regions; a second circuit area having second fin active regions extending lengthwise along the first direction, each of the second fin active regions includes second channel regions; a gate connector area between and separating the first and the second circuit areas, the gate connector area having filter fins extending lengthwise along the first direction; and a gate structure extending across the first circuit area, the gate connector area, and the second circuit area along a second direction over the first and second channel regions and the filter fins. A portion of the gate structure in the gate connector area has a greater resistivity than portions of the gate structure in the first and the second circuit areas.

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes: a substrate, a first circuit region and a second circuit region extending in a first direction, and a gate structure extending in a second direction that is substantially perpendicular to the first direction. The gate structure further includes: two gate electrode sections respectively located in the first and second circuit regions, and a low-resistance section between and interconnecting the two gate electrode sections. The two gate electrode sections are configured as gate electrodes for two transistors respectively located in the first and second circuit regions. The two gate electrodes have a first width (W0) along the first direction, the low-resistance section has a second width (W) along the first direction, and a ratio of W to W0 (W/W0) is at least 1.1.