Abstract: A method for multi-link operation (MLO) is provided. The method for MLO may be applied to an apparatus. The method for MLO may include the following steps. A multi-chip controller of the apparatus may assign different data to a plurality of chips of the apparatus, wherein each chip corresponds to one link of multi-links. Each chip may determine whether transmission of the assigned data has failed. A first chip of the chips may transmit the assigned data to an access point (AP) in response to the first chip determining that the transmission of the assigned data has not failed.

Abstract: A semiconductor structure includes a semiconductor element and a first bonding structure. The semiconductor element has a first surface and a second surface opposite to the first surface. The first bonding structure is disposed adjacent to the first surface of the semiconductor element, and includes a first electrical connector, a first insulation layer surrounding the first electrical connector and a first conductive layer surrounding the first insulation layer.

Abstract: In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.

Abstract: A storage device stores rows of bits including a D0 bit, an X0 bit, an X1 bit, a Y0 bit, a Y1 bit and a spatially predicted coded block pattern having an A0 bit, an A1 bit, an A2 bit, and an A3 bit. A first circuit is connected to the storage device for setting the A0 bit. A second circuit is connected to the storage device for setting the A2 bit and operates in parallel to the first circuit. In a second clock cycle, the bits in the storage device are shifted and the first circuit and the second circuit are reused to calculate the A1 bit and the A2 bit in parallel. Alternatively, a third circuit and a fourth circuit can be connected to the storage device to calculate the A1 bit and the A2 bit in parallel during the first clock cycle.

Abstract: A highly integrated MPEG-4 video decoding unit includes switching circuit, a set of decoding modules, and a memory. The set of decoding modules includes a plurality of decoding modules, each capable of decoding a predetermined signal in each of a plurality of VOP types. The decoding module may include a VOP type indicating flag that is set by the switching circuit so that the correct lookup table can be used during decoding of the predetermined signal. Alternatively, the necessary lookup table(s) may be electronically transferred to the corresponding decoding module. According to the type of VOP being decoded, the switching circuit may send a predetermined sequence of selection signals to a multiplexer so that the decoded results from appropriate decoding modules are stored into the corresponding storage elements in the memory.

Abstract: A method for using memory to store motion vectors of decoded macroblocks as candidate predictors used in future motion vector decoding process. For a decoded first macroblock, the method allocates a first memory space and a second memory space in a first memory, and allocates a third memory space and a fourth memory space in a second memory for storing the motion vector(s) of the first macroblock. When allocating memory spaces in the first memory, the method considers a row of macroblocks in the video frame as a whole, and allocates a plurality of memory units that are sufficient for storing motion vectors of a row of macroblocks. During the process of decoding each row of macroblocks, the memory units of the first memory can be re-used to store motion vectors of decoded macroblocks.

Abstract: A storage device stores rows of bits including a D0 bit, an X0 bit, an X1 bit, a Y0 bit, a Y1 bit and a spatially predicted coded block pattern having an A0 bit, an A1 bit, an A2 bit, and an A3 bit. A first circuitis connected to the storage device for setting the A0 bit. A second circuitis connected to the storage device for setting the A2 bit and operates in parallel to the first circuit. In a second clock cycle, the bits in the storage device are shifted and the first circuit and the second circuit are reused to calculate the A1 bit and the A2 bit in parallel. Alternatively, a third circuit and a fourth circuit can be connected to the storage device to calculate the A1 bit and the A2 bit in parallel during the first clock cycle.

Abstract: A predictive decoding method includes (a) storing a plurality of first vertical predictors of a first block into a storing column of a first memory device, and storing a plurality of first horizontal predictors of a second block into a storing row of the first memory device; (b) performing a prediction operation for generating a plurality of target vertical predictors and a plurality of target vertical predictors of a target block according to the first vertical predictors and the first horizontal predictors, wherein the target block is adjacent to the first and second blocks, and the first and target blocks are located at the same row; and (c) updating the storing column of the first memory device by the target vertical predictors, and updating the storing row of the first memory device by the target horizontal predictors.