Patents by Inventor Hui Hui Ngu

Hui Hui Ngu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Configurable first in first out and deserializer circuitry
    Patent number: 10771063
    Abstract: An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites, such as by filling via opening and/or using jumpers, may form a deserializer circuit with a first via configuration or a first-in first-out (FIFO) circuit with a second via configuration.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Eah Loon Alan Chuah, Hui Hui Ngu
  • Configurable First In First Out and Deserializer Circuitry
    Publication number: 20190319628
    Abstract: An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites, such as by filling via opening and/or using jumpers, may form a deserializer circuit with a first via configuration or a first-in first-out (FIFO) circuit with a second via configuration.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Inventors: Eah Loon Alan Chuah, Hui Hui Ngu
  • ROM segmented bitline circuit
    Patent number: 9704874
    Abstract: A bitline structure for use in a memory device may be connected to a plurality of bit memory cells. The bitline may be segmented into segments connected to one-third of the plurality of bit memory cells and two-thirds of the bit memory cells, respectively. The segments may be electrically coupled to each other to provide an overall bitline output.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: July 11, 2017
    Assignee: eASIC Corporation
    Inventors: Ban P. Wong, Hui Hui Ngu
  • ROM SEGMENTED BITLINE CIRCUIT
    Publication number: 20170170186
    Abstract: A bitline structure for use in a memory device may be connected to a plurality of bit memory cells. The bitline may be segmented into segments connected to one-third of the plurality of bit memory cells and two-thirds of the bit memory cells, respectively. The segments may be electrically coupled to each other to provide an overall bitline output.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 15, 2017
    Inventors: Ban P. WONG, Hui Hui NGU
  • Configurable write policy in a memory system
    Patent number: 8040739
    Abstract: A configurable memory system may be able to support at least three different write policies, namely, no-read-on-write, read-before-write, and read-after-write. Such a system may include configurable write signal timing, configurable read signal timing, and/or configurable wordline enable signal timing. Static and/or dynamic configuration of the system may be used.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: October 18, 2011
    Assignee: eASIC Corporation
    Inventors: Hui Hui Ngu, Choon Keat Khor
  • Configurable Write Policy in a Memory System
    Publication number: 20100195419
    Abstract: A configurable memory system may be able to support at least three different write policies, namely, no-read-on-write, read-before-write, and read-after-write. Such a system may include configurable write signal timing, configurable read signal timing, and/or configurable wordline enable signal timing. Static and/or dynamic configuration of the system may be used.
    Type: Application
    Filed: February 3, 2009
    Publication date: August 5, 2010
    Applicant: eASIC CORPORATION
    Inventors: Hui Hui Ngu, Choon Keat Khor
  • Multiple write during simultaneous memory access of a multi-port memory device
    Patent number: RE46474
    Abstract: A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 11, 2017
    Assignee: eASIC CORPORATION
    Inventors: Hui Hui Ngu, Bruce Gieseke