Abstract: A method for multi-link operation (MLO) is provided. The method for MLO may be applied to an apparatus. The method for MLO may include the following steps. A multi-chip controller of the apparatus may assign different data to a plurality of chips of the apparatus, wherein each chip corresponds to one link of multi-links. Each chip may determine whether transmission of the assigned data has failed. A first chip of the chips may transmit the assigned data to an access point (AP) in response to the first chip determining that the transmission of the assigned data has not failed.

Abstract: A color conversion panel and a display device are provided. The color conversion panel includes an opaque substrate and a sapphire substrate. The opaque substrate includes a plurality of first pixel openings, a plurality of second pixel openings and a plurality of third pixel openings. The first pixel openings are filled with red quantum dot material, and the second pixel openings are filled with green quantum dot material. The sapphire substrate is on the opaque substrate. A first surface of the sapphire substrate that faces the opaque substrate has a plurality of first arc surfaces corresponding to the first pixel openings, a plurality of second arc surfaces corresponding to the second pixel openings, and a plurality of third arc surfaces corresponding to the third pixel openings.

Abstract: A display device and a projector are provided. The display device includes a pixel light-emitting panel and multiple color conversion panels. The pixel light-emitting panel includes an N1 number of light-emitting pixel units distributed in an array, and the light-emitting pixel units are driven to emit light through a driver. A first color conversion panel includes an N2 number of first color pixels and an N3 number of first transparent pixels. The first color pixels and the first transparent pixels are disposed relative to the light-emitting pixel units. A second color conversion panel includes an N4 number of second color pixels and an N5 number of second transparent pixels. The second color pixels and the second transparent pixels are disposed relative to the light-emitting pixel units. The lights generated by at least part of the light-emitting pixel units sequentially pass through the first color pixels and the second transparent pixels to achieve the color conversion.

Abstract: A method of fabricating a flash memory includes providing a semiconductor substrate with STIs and an active area between two adjacent STIs along a first direction; successively forming a floating-gate insulating layer, a conductive layer, a dielectric layer, a control gate, and a cap layer on the semiconductor substrate; forming spacers on the sidewalls of the cap layer and the control gate; removing the dielectric layer, the conductive layer, and the floating-gate insulating layer not covered by the spacers and the cap layer; performing a selective epitaxial growth process to form an epitaxial layer on the exposed semiconductor substrate in the active area; and forming a source in the epitaxial layer and the semiconductor substrate in the active area.

Abstract: A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer. Then, a portion of the floating gate layer is removed from the openings to form sunken regions on the surface of the floating gate layer. An inter-gate dielectric layer is formed on the floating gate layer. A control gate layer is formed on the inter-gate dielectric layer. After that, the mask layer and the floating gate layer under the mask layer are removed to form another opening. A select gate layer is formed inside the opening.

Abstract: A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer. Then, a portion of the floating gate layer is removed from the openings to form sunken regions on the surface of the floating gate layer. An inter-gate dielectric layer is formed on the floating gate layer. A control gate layer is formed on the inter-gate dielectric layer. After that, the mask layer and the floating gate layer under the mask layer are removed to form another opening. A select gate layer is formed inside the opening.

Abstract: A multi-level split-gate flash memory is provided. The flash memory includes a substrate, a memory row, a dummy select gate, a source region and a drain region. The memory cell row includes a plurality of serially connected memory cells with each memory cell having a stacked gate structure and a select gate at least. The stacked gate structure of each memory cell is disposed on the substrate. The select gate is disposed on a sidewall of the stacked gate structure. The dummy select gate is disposed on one side of the memory cell row adjacent to the sidewall of the stacked gate structure at the end of the memory cell row. The source region and the drain region are disposed in the substrate beside the dummy select gate and the memory cell row.