Abstract: Disclosed is a semiconductor device comprising an active pattern including first and second edge parts spaced apart from each other in a first direction, a word line extending along a second direction between the first and second edge parts, a bit line extending along a third direction on the first edge part, a storage node contact on the second edge part, a first active pad between the bit line and the first edge part, and a second active pad between the storage node contact and the second edge part. The first active pad extends in the third direction more than the first edge part. The second active pad extends in a direction opposite to the third direction more than the second edge part.

Abstract: A semiconductor memory device includes active regions including first impurity regions and second impurity regions, word lines on the active regions and extended in a first direction, bit lines on the word lines and extended in a second direction crossing the first direction, the bit lines being connected to the first impurity regions, first contact plugs between the bit lines, the first contact plugs being connected to the second impurity regions, landing pads on the first contact plugs, respectively, and gap-fill structures filling spaces between the landing pads, top surfaces of the gap-fill structures being higher than top surfaces of the landing pads.

Abstract: A semiconductor memory device includes a substrate comprising an element isolation layer, a bit line that extends on the substrate in a first direction, a cell buffer insulating layer between the bit line and the substrate and comprising an upper cell buffer insulating layer and a lower cell buffer insulating layer, a lower storage contact disposed on a plurality of sides of the bit line and comprising a semiconductor epitaxial pattern, a storage pad on the lower storage contact and connected to the lower storage contact and an information storage unit on the storage pad and connected to the storage pad, wherein the upper cell buffer insulating layer is between the lower cell buffer insulating layer and the bit line, and each of the lower cell buffer insulating layer and the upper cell buffer insulating layer comprises an upper surface and a lower surface that are opposite to each other.

Abstract: A semiconductor memory device comprising: a substrate including active patterns; a gate structure intersecting the active patterns; bit-line structures on the substrate; first contacts, wherein the bit-line structures and the first contacts are alternately arranged with each other; insulating patterns respectively disposed on the bit-line structures, wherein an insulating pattern among the insulating patterns is disposed in a first trench exposing a sidewall of a first contact among the first contacts and at least a portion of the gate structure; and second contacts disposed on the first contacts, wherein a second contact among the second contacts is disposed in a second trench exposing a sidewall of the insulating pattern and an upper surface of the first contact, wherein the insulating pattern overlaps an upper surface of a bit-line structure among the bit-line structures and extends along sidewalls of the first and second trenches and contacts the first and second contacts.

Abstract: There is provided a semiconductor memory device comprising: a substrate; a base insulating film on an upper surface of the substrate; a plurality of first conductive patterns on the base insulating film and spaced apart from each other, wherein the plurality of first conductive patterns extend in a first direction; a spacer structure on a side surface of each of the plurality of first conductive patterns; a barrier metal film on a side surface of the spacer structure, wherein the barrier metal film extends through the base insulating film to be electrically connected to the substrate; a filling metal film on the barrier metal film, wherein the filling metal film fills at least a portion of a space between adjacent ones of the plurality of first conductive patterns; and a capacitor structure on the filling metal film, wherein the capacitor structure is electrically connected to the filling metal film.

Abstract: A semiconductor memory device include first and second active patterns extending in a first direction and spaced apart from each other in a second direction crossing the first direction. The first and second active patterns include a first and second edge portions spaced apart from each other in the first direction, and a center portion therebetween. Bit line node contacts are on the center portions. Bit lines are on the bit line node contacts and extend in a third direction crossing the first and second directions. The center portions of the first and second active patterns are sequentially disposed in the second direction. Each of the bit line node contacts has a first width at a level of a top surface, a second width at a level of a bottom surface, and a third width between the top and bottom surfaces less than the first and second widths.

Abstract: An example semiconductor memory device includes first and second active patterns, which are extended in a first direction and are disposed side by side in a second direction. Each of the first and second active patterns includes first and second edge portions, which are spaced apart from each other in the first direction. A pair of word lines are disposed to cross each of the first and second active patterns, a pair of bit lines are disposed on each of the first and second active patterns and are extended in a third direction, and a storage node contacts on the first edge portion of the first active pattern. When measured in the second direction, a first width of the storage node contact at a first level is larger than a second width at a second level. The first level is lower than the second level.

Abstract: A semiconductor device includes first and second active patterns extending in a first direction and arranged in a second direction intersecting the first direction, each of the first and second active patterns including first and second edge portions spaced apart from each other in the first direction, a first storage node pad and a first storage node contact sequentially provided on the first edge portion of the first active pattern, and a second storage node pad and a second storage node contact sequentially provided on the second edge portion of the second active pattern. Each of the first and second storage node contacts includes a metal material.

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a lower substrate, a lower dielectric structure on the lower substrate, a memory cell structure between the lower substrate and the lower dielectric structure, a lower bonding pad in the lower dielectric structure, an upper dielectric structure on the lower dielectric structure, an upper substrate on the upper dielectric structure, a transistor between the upper substrate and the upper dielectric structure, and an upper bonding pad in the upper dielectric structure. A top surface of the lower bonding pad is in contact with a bottom surface of the upper bonding pad. The lower bonding pad and the upper bonding pad overlap the memory cell structure.

Abstract: A semiconductor device includes first and second active patterns extending in a first direction and being adjacent to each other in a second direction, the first and second active patterns, each of which includes first and second edges spaced apart from each other in the first direction, a first storage node pad and a first storage node contact sequentially provided on the first edge of the first active pattern, a second storage node pad and a second storage node contact sequentially provided on the second edge of the second active pattern, and a fence pattern between the first and the second storage node contacts. Bottom and top surfaces of the first storage node contact are located at first and second levels, respectively. In a third direction, a width of the fence pattern at the first level is less than a width of the fence pattern at the second level.

Abstract: A semiconductor device includes a device isolation part on a substrate and defining active regions that are two-dimensionally disposed in first and second directions, the active regions each extending in the first direction; first and second word lines crossing the active regions in the second direction and adjacent to each other in the first direction; a first impurity region in the active region between the first and second word lines; a second impurity region in the active region at one side of the first word line and spaced apart from the first impurity region; a first conductive pad in contact with the first impurity region; a second conductive pad in contact with the second impurity region; a bit line on the first conductive pad and extending in the first direction; a storage node contact structure on the second conductive pad; and a landing pad on the storage node contact structure.

Abstract: A semiconductor memory device includes active regions including first impurity regions and second impurity regions, word lines on the active regions and extended in a first direction, bit lines on the word lines and extended in a second direction crossing the first direction, the bit lines being connected to the first impurity regions, first contact plugs between the bit lines, the first contact plugs being connected to the second impurity regions, landing pads on the first contact plugs, respectively, and gap-fill structures filling spaces between the landing pads, top surfaces of the gap-fill structures being higher than top surfaces of the landing pads.

Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

Abstract: A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.

Abstract: A semiconductor device including: a device isolation part on a substrate to define first to fourth active regions, the device isolation part interposed between the first and second active regions and the third and fourth active regions; first and second word lines crossing the first and second active regions and adjacent to each other; a first impurity region in the first active region between the first and second word lines; a second impurity region in the first active region at one side of the first word line and spaced apart from the first impurity region; a first conductive pad contacting the first impurity region; a second conductive pad contacting the second impurity region; a bit line on the first conductive pad; a storage node contact on the second conductive pad; and a landing pad on the storage node contact.

Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

Abstract: Provided is a semiconductor memory device comprising an active region extending in a cell isolation layer, wherein the active region includes a first region and a second region; a bit line intersects the active region; a bit line contact between a substrate and the bit line, wherein the bit line contact is electrically connected to the first region; a bit line spacer that is on side surfaces of the bit line and the bit line contact; a node pad on a lateral side of the bit line spacer, wherein the node pad is electrically connected to the second region; a storage contact that is on the node pad and on a side surface of the bit line spacer, wherein the storage contact includes a first part having a first width and a second part having a second width different from the first width.

Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.

Abstract: A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.