Patents by Inventor Hui-Jung Tsai
Hui-Jung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961811Abstract: A semiconductor structure includes a semiconductor element and a first bonding structure. The semiconductor element has a first surface and a second surface opposite to the first surface. The first bonding structure is disposed adjacent to the first surface of the semiconductor element, and includes a first electrical connector, a first insulation layer surrounding the first electrical connector and a first conductive layer surrounding the first insulation layer.Type: GrantFiled: June 14, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hung-Jui Kuo, Hui-Jung Tsai, Tsao-Lun Chang
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Publication number: 20240105901Abstract: In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: Chen-Hua Yu, Keng-Han Lin, Hung-Jui Kuo, Hui-Jung Tsai
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Publication number: 20240096787Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Ming-Da CHENG, Wei-Hung LIN, Hui-Min HUANG, Chang-Jung HSUEH, Po-Hao TSAI, Yung-Sheng LIN
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Publication number: 20230417968Abstract: A display module has a touch display area, a non-touch display area and a frame area surrounding them. The display module includes a cover plate, an ink layer, a touch display panel, a non-touch display panel and an optical matching layer. The ink layer is disposed on the cover plate and corresponds to the frame area. The touch display panel and the non-touch display panel are disposed on a side of the ink layer opposite to the cover plate and respectively correspond to the touch display area and the non-touch display area. The optical matching layer is disposed between the cover plate and one of the touch display panel and the non-touch display panel. A difference of average reflectance to external light between any two of the above areas is less than 1.5%, and a chromaticity difference between any two of the above areas is less than 1.5.Type: ApplicationFiled: May 19, 2023Publication date: December 28, 2023Applicant: HENGHAO TECHNOLOGY CO., LTD.Inventors: Wen-Jung Tsai, Hui-Jung Tsai, Ching-Yu Tsai
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Patent number: 11855246Abstract: In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.Type: GrantFiled: October 25, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Keng-Han Lin, Hung-Jui Kuo, Hui-Jung Tsai
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Publication number: 20230384684Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.Type: ApplicationFiled: July 25, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang
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Publication number: 20230378111Abstract: A semiconductor structure includes a semiconductor substrate, a first electrical connector, a first electrical connector and a dielectric material. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The first electrical connector is disposed over the first surface of the semiconductor substrate. The second electrical connector is electrically connected to the first electrical connector, and the first electrical connector surrounds the second electrical connector. The dielectric material is disposed between the first electrical connector and the second electrical connector.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hung-Jui Kuo, Hui-Jung Tsai, Tsao-Lun Chang
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Patent number: 11823969Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.Type: GrantFiled: June 30, 2022Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
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Patent number: 11823936Abstract: An alignment holder for holding a composite specimen includes a holder body and a positioning mechanism. The holder body is configured to clamp a first side of the composite specimen therein. The positioning mechanism is movably engaged with the holder body. The positioning mechanism is configured to lean against a second side of the composite specimen and move relatively to the holder body for adjusting a clamping position of the composite specimen clamped by the holder body.Type: GrantFiled: April 13, 2022Date of Patent: November 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih Wang, Hung-Jui Kuo, Hui-Jung Tsai
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Publication number: 20230369153Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.Type: ApplicationFiled: July 28, 2023Publication date: November 16, 2023Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
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Publication number: 20230352442Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: ApplicationFiled: July 10, 2023Publication date: November 2, 2023Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Patent number: 11789366Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.Type: GrantFiled: June 1, 2022Date of Patent: October 17, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang
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Patent number: 11756879Abstract: A semiconductor device includes a die, a plurality of dielectric layers over the die, a via and at least one ring. The dielectric layers include a plurality of first surfaces facing the die. The via penetrates through the plurality of dielectric layers and includes at least one second surface facing the die. The ring surrounds the via and is disposed in at least one of the plurality of dielectric layers. The ring includes a third surface facing the die, wherein the third surface of the at least one ring is inserted between the at least one second surface of the via and the first surface of the at least one of the plurality of dielectric layers.Type: GrantFiled: August 6, 2021Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Keng-Han Lin, Jyun-Siang Peng
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Publication number: 20230275030Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.Type: ApplicationFiled: April 19, 2023Publication date: August 31, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
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Publication number: 20230274976Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.Type: ApplicationFiled: April 18, 2023Publication date: August 31, 2023Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
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Patent number: 11742317Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: GrantFiled: October 17, 2019Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Publication number: 20230260898Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. The at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. The insulating encapsulant is encapsulating the at least one semiconductor die. The redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. The redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
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Publication number: 20230207478Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Chen-Hua Yu, Hui-Jung Tsai
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Patent number: 11670582Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. The at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. The insulating encapsulant is encapsulating the at least one semiconductor die. The redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. The redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.Type: GrantFiled: February 14, 2022Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
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Patent number: 11664325Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.Type: GrantFiled: February 8, 2022Date of Patent: May 30, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng