Patents by Inventor Hui-Jung Tsai

Hui-Jung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250087627
    Abstract: A method of forming a semiconductor package includes the following operations. A first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. A plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. A second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. The second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.
    Type: Application
    Filed: November 26, 2024
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chia-Wei Wang, Yu-Tzu Chang
  • Publication number: 20250060676
    Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang
  • Publication number: 20250029946
    Abstract: A package structure includes an integrated circuit die and an encapsulant laterally encapsulating the integrated circuit die. The integrated circuit die includes a semiconductor substrate, an interconnection structure, a testing pad, a dummy post, a conductive post, and a protection layer. The interconnection structure is disposed on the semiconductor substrate. The testing pad is disposed on the interconnection structure. The dummy post is disposed on the testing pad. The conductive post is aside the dummy post. The protection layer is disposed between the conductive post and the dummy post.
    Type: Application
    Filed: October 3, 2024
    Publication date: January 23, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
  • Patent number: 12176321
    Abstract: A method of forming a semiconductor package includes the following operations. A first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. A plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. A second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. The second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chia-Wei Wang, Yu-Tzu Chang
  • Patent number: 12165985
    Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chen-Hua Yu, Hui-Jung Tsai, Hung-Jui Kuo, Chung-Shi Liu, Han-Ping Pu, Ting-Chu Ko
  • Patent number: 12164232
    Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang
  • Publication number: 20240387392
    Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chen-Hua Yu, Hui-Jung Tsai, Hung-Jui Kuo, Chung-Shi Liu, Han-Ping Pu, Ting-Chu Ko
  • Publication number: 20240387789
    Abstract: In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chen-Hua Yu, Keng-Han Lin, Hung-Jui Kuo, Hui-Jung Tsai
  • Publication number: 20240387450
    Abstract: A redistribution structure includes a first dielectric layer, a second dielectric layer, and a first metallization pattern. The second dielectric layer is located on the first dielectric layer. The first metallization pattern is located between the first dielectric layer and the second dielectric layer. The first metallization pattern includes a first seed layer and a first conductive material on the first seed layer to form a first conductive via, a first conductive line, and a second conductive via. The first conductive via is located in the first dielectric layer. The first conductive line is located in the second dielectric layer, and between the first conductive via and the second conductive via. The second conductive via is located on the first conductive line and in the second dielectric layer.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chia-Wei Wang, Yu-Tzu Chang
  • Patent number: 12148732
    Abstract: A method of forming a redistribution structure includes providing a dielectric layer. The dielectric layer is patterned to form a plurality of via openings. A seed layer is formed on the dielectric layer and filling in the plurality of via openings. A patterned conductive layer is formed a on the seed layer, wherein a portion of the seed layer is exposed by the patterned conductive layer. The portion of the seed layer is removed by using an etching solution, thereby forming a plurality of conductive lines and a plurality of vias. During the removing the portion of the seed layer, an etch rate of the patterned conductive layer is less than an etch rate of the seed layer.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chia-Wei Wang, Yu-Tzu Chang
  • Publication number: 20240363450
    Abstract: Provided is a method of detecting photoresist scums and photoresist residues. A carrier is provided. The carrier has a photoresist layer with opening patterns therein. A plasma etching process is performed to the opening patterns of the photoresist layer. Charges are injected to the opening patterns of the photoresist layer. Whether a photoresist scum or residue is present in at least one of the opening patterns is detected.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chih Wang
  • Patent number: 12132023
    Abstract: An integrated circuit includes a semiconductor substrate, contact pads, testing pads, conductive posts, dummy posts, and a protection layer. The contact pads and the testing pads are distributed over the semiconductor substrate. The conductive posts are disposed on the contact pads. The dummy posts are disposed on the testing pads and are electrically floating. The protection layer covers the conductive posts and the dummy posts. A distance between top surfaces of the conductive posts and a top surface of the protection layer is smaller than a distance between top surfaces of the dummy posts and the top surface of the protection layer.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
  • Publication number: 20240321765
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Publication number: 20240304542
    Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. The at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. The insulating encapsulant is encapsulating the at least one semiconductor die. The redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. The redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.
    Type: Application
    Filed: May 16, 2024
    Publication date: September 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
  • Patent number: 12080609
    Abstract: Provided is a method of detecting photoresist scums and photoresist residues. A carrier is provided. The carrier has a photoresist layer with opening patterns therein. A plasma etching process is performed to the opening patterns of the photoresist layer. Charges are injected to the opening patterns of the photoresist layer. Whether a photoresist scum or residue is present in at least one of the opening patterns is detected.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: September 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chih Wang
  • Publication number: 20240282653
    Abstract: Provided is a package structure including a first die and an encapsulant. The first die includes a substrate, a plurality of pads over the substrate, a passivation layer on portions of each of the plurality of pads, a plurality of first die connectors on the plurality of pads, respectively and a dielectric layer laterally encapsulating the plurality of first die connectors. The encapsulant laterally encapsulates the first die. One of the plurality of first die connectors is a taper-shaped die connector. A width of the one of the plurality of first die connectors gradually increases from a top surface of the one of the plurality of first die connectors toward the a top surface of the passivation layer.
    Type: Application
    Filed: May 1, 2024
    Publication date: August 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
  • Publication number: 20240274567
    Abstract: A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.
    Type: Application
    Filed: April 25, 2024
    Publication date: August 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Jyun-Siang Peng
  • Patent number: 12062603
    Abstract: Embodiments include plating a contact feature in a first opening in a mask layer, the contact feature physically coupled to a contact pad, the contact feature partially filling the first opening. A solder cap is directly plated onto the contact feature in the first opening. The mask layer is then removed to expose an upper surface of a work piece, the contact feature vertically protruding from the work piece. After utilizing the solder cap, etching the solder cap to remove the solder cap from over the contact feature. A first encapsulant is deposited laterally around and over an upper surface of the contact feature. The first encapsulant is planarized to level an upper surface of the first encapsulant with the upper surface of the contact feature.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo
  • Patent number: 12040283
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Patent number: 12020983
    Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu