Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: The embodiments of the invention provide a multi-focal collimating lens and a headlight assembly for an automotive low beam. The multi-focal collimating lens includes a central collimating lens portion and two total internal reflection lens portions arranged on a left side and a right side of the central collimating lens portion. The central collimating lens portion and the total internal reflection lens portions share two focal points symmetrically located on both sides of a vertical symmetry plane of the multi-focal collimating lens. An upper edge and a lower edge of the multi-focal collimating lens are formed based on the two focal points, so that the headlight assembly is able to generate a cut-off line of the automotive low beam in a far-field light pattern of the multi-focal collimating lens.

Abstract: The embodiments of the invention provide a multi-focal collimating lens and a headlight assembly for an automotive low beam. The multi-focal collimating lens includes a central collimating lens portion and two total internal reflection lens portions arranged on a left side and a right side of the central collimating lens portion. The central collimating lens portion and the total internal reflection lens portions share two focal points symmetrically located on both sides of a vertical symmetry plane of the multi-focal collimating lens. An upper edge and a lower edge of the multi-focal collimating lens are formed based on the two focal points, so that the headlight assembly is able to generate a cut-off line of the automotive low beam in a far-field light pattern of the multi-focal collimating lens.

Abstract: The present disclosure provides a light emitting module including: a substrate supporting at least one light emitting component; an enclosing component surrounding the light emitting component and defining an interspace between an inner surface of the enclosing component and the light emitting component; a coating material applied in the interspace between the enclosing component and the light emitting component. The enclosing component is attached as a separate component on the substrate. The light emitting module according to the present disclosure has an improved manufacturing effectiveness and convenience, and less complexity, thus reducing the production cost.

Abstract: The disclosure provides a light-emitting diode (LED) package structure, including: a lead frame; at least two light-emitting diode chips having different light-emitting wavelengths disposed on the lead frame; an encapsulant disposed over the lead frame and covering the light-emitting diode chips, wherein the encapsulant has a first concave portion; and an optical glue disposed in the first concave portion, wherein the optical glue has a plurality of scattering particles to uniformly mix the lights of different wavelengths emitted by the light-emitting diode chips.