Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows, a temperature sensor that detects a temperature of the memory cell array and generates internal temperature data, a first register that stores external temperature data received from outside of the memory device, and a refresh control unit that determines a skip ratio of refresh commands received at a refresh frequency that corresponds to the external temperature data by comparing the internal temperature data and the external temperature data and performing a refresh operation for the plurality of memory cell rows in response to refresh commands skipped and transmitted based on the skip ratio.

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows, a temperature sensor that detects a temperature of the memory cell array and generates internal temperature data, a first register that stores external temperature data received from outside of the memory device, and a refresh control unit that determines a skip ratio of refresh commands received at a refresh frequency that corresponds to the external temperature data by comparing the internal temperature data and the external temperature data and performing a refresh operation for the plurality of memory cell rows in response to refresh commands skipped and transmitted based on the skip ratio.

Abstract: A memory device includes a memory bank, a row selection circuit and a refresh controller. The memory bank includes a plurality of memory blocks, and each memory block includes a plurality of memory cells arranged in rows and columns. The row selection circuit performs an access operation with respect to the memory bank and a hammer refresh operation with respect to a row that is physically adjacent to a row that is accessed intensively. The refresh controller controls the row selection circuit such that the hammer refresh operation is performed during a row active time for the access operation. The hammer refresh operation may be performed efficiently and performance of the memory device may be enhanced by performing the hammer refresh operation during the row active time for the access operation.

Abstract: A memory device is provided which is capable of adjusting an operation voltage, and an application processor is provided for controlling the memory device. The memory device may include: a receiving terminal for receiving a voltage control signal from an external source, the voltage control signal being for adjusting an operation voltage level according to an operation speed of the memory device; and a voltage adjustment unit for adjusting a level of an operation voltage of the memory device in response to the voltage control signal. The level of the operation voltage is adjusted before a memory operation is performed at the operation speed corresponding to the adjusted operation voltage.

Abstract: A memory device is provided which is capable of adjusting an operation voltage, and an application processor is provided for controlling the memory device. The memory device may include: a receiving terminal for receiving a voltage control signal from an external source, the voltage control signal being for adjusting an operation voltage level according to an operation speed of the memory device; and a voltage adjustment unit for adjusting a level of an operation voltage of the memory device in response to the voltage control signal. The level of the operation voltage is adjusted before a memory operation is performed at the operation speed corresponding to the adjusted operation voltage.

Abstract: A memory device includes a memory bank, a row selection circuit and a refresh controller. The memory bank includes a plurality of memory blocks, and each memory block includes a plurality of memory cells arranged in rows and columns. The row selection circuit performs an access operation with respect to the memory bank and a hammer refresh operation with respect to a row that is physically adjacent to a row that is accessed intensively. The refresh controller controls the row selection circuit such that the hammer refresh operation is performed during a row active time for the access operation. The hammer refresh operation may be performed efficiently and performance of the memory device may be enhanced by performing the hammer refresh operation during the row active time for the access operation.

Abstract: A memory device includes a memory bank, a command control logic circuit, a row selection circuit, a refresh controller and a collision controller. The memory bank includes a plurality of memory blocks. The command control logic circuit decodes commands received from a memory controller to generate control signals. The command control logic receives an active command for an access operation during a refresh operation. The row selection circuit performs the access operation and the refresh operation with respect to the memory bank. The refresh controller controls the refresh operation. The collision controller generates a wait signal causing a delay of the access operation based on a result of a comparison of a row address associated with the access operation and a refresh address associated with the refresh operation.

Abstract: In a system including a power management integrated circuit (PMIC) and a memory device, an application processor obtains control information for a memory device, the control information defining in part at least a first power supply voltage and operating clock frequency for the memory device. A memory control unit (MCU) communicates a workload indication related to queued operation commands for the memory device to a digital voltage and frequency scaling (DVFS) controller, and the DVFS controller provides a power supply voltage command to the PMIC in response to the MCU workload indication and the control information.

Abstract: A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided.

Abstract: A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided.

Abstract: A memory device for early stabilization and rapid increase of a power level after deep power down exit includes a deep power down exit pulse generator, a deep power down exit mode signal generator, a current driving unit, a controller and a voltage generator. The deep power down exit pulse generator generates a deep power down exit pulse signal having a predetermined pulse width in response to a deep power down command. The deep power down exit mode signal generator generates a deep power down exit mode bias signal in response to the deep power down exit pulse signal. The current driving unit generates a deep power down exit mode reference voltage in response to the deep power down exit mode bias signal and a reference signal. The controller generates an enable signal in response to the deep power down exit mode bias signal or an active command.

Abstract: Provided are a boosted voltage detecting circuit capable of reducing the consumption of current and reducing ripple in boosted voltage during a self-refresh operation of a semiconductor memory device, and a method of controlling the same. One embodiment of the boosted voltage detecting circuit includes a feedback unit feeding back a boosted voltage, a reference voltage receiving unit receiving a reference voltage, and a detection signal generating unit comparing output voltages received from the feedback and reference voltage receiving units and generating a detection signal according to the result of comparison.

Abstract: Provided are a boosted voltage detecting circuit capable of reducing the consumption of current and reducing ripple in boosted voltage during a self-refresh operation of a semiconductor memory device, and a method of controlling the same. One embodiment of the boosted voltage detecting circuit includes a feedback unit feeding back a boosted voltage, a reference voltage receiving unit receiving a reference voltage, and a detection signal generating unit comparing output voltages received from the feedback and reference voltage receiving units and generating a detection signal according to the result of comparison.

Abstract: A level shifter circuit and method thereof are provided. The example level shifter circuit may include a pull-up drive unit driving an output node from a first voltage to a second voltage in response to an input signal, a target voltage for the second voltage higher than a target voltage for the first voltage and the input signal based on the first voltage and a third voltage and a pull-down drive unit driving the output node to the third voltage in response to the input signal, the pull-up and pull-down drive units adjusting current levels of at least one of a pull-up current flowing through the pull-up drive unit and a pull-down current flowing through the pull-down drive unit based on whether the pull-up drive unit and the pull-down drive unit are operating concurrently.