Abstract: Provided are: a method for modifying a target nucleic acid in the genome of a cell using a novel PAM sequence; and a cell in which a target nucleic acid in the genome is modified thereby. Accordingly, genome editing can be performed by targeting a position that could not be previously targeted as a target for genome editing, and thus the range of applications of genome editing can be expanded.

Abstract: A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.

Abstract: A system for predicting prime editing efficiency by using deep learning, including: an information input unit that receives an input of data on prime editing efficiency of a prime editor, a predictive model generator for generating prime editing efficiency predictive models by performing deep learning to learn a relationship between features affecting prime editing efficiency and prime editing efficiency, by using the data received from the information input unit, a candidate sequence input unit that receives an input of a candidate target sequence for prime editing; and an efficiency predictor for predicting prime editing efficiency by applying the candidate target sequence input into the candidate sequence input unit to an efficiency predictive model generated in the predictive model generator.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: Provided are: a method of modifying a target nucleic acid in the genome of a cell by using a novel PAM sequence; and a cell in which a target nucleic acid of the genome of the cell is modified by the method. Accordingly, genome editing may be performed by targeting a position, which has not been previously targeted, as a target for genome editing, and thus the range of applications of genome editing may be expanded.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.

Abstract: Provided are: a method for modifying a target nucleic acid in the genome of a cell using a novel PAM sequence; and a cell in which a target nucleic acid in the genome is modified thereby. Accordingly, genome editing can be performed by targeting a position that could not be previously targeted as a target for genome editing, and thus the range of applications of genome editing can be expanded.

Abstract: An active suspension control unit may include an actuator having an active roll stabilization (ARS) structure to variably adjust response characteristics of a suspension, and a controller for determining a driving situation of a vehicle through information input from a sensor, and determining a final desired control value of the actuator based on a desired relative suspension vertical force value set in advance according to the driving situation and a difference value generated by a difference between left and right wheel's relative suspension vertical velocities.

Abstract: A semiconductor integrated card includes an external package, a subscriber identification module (SIM) circuit, a plurality of SIM pins, a storage device and a plurality of memory pins. The SIM circuit is formed inside of the external package and is configured to store subscriber information. The SIM pins are formed on a surface of the external package and are electrically connected to the SIM circuit. The storage device is formed inside of the external package and is separated from the SIM circuit. The storage device includes a nonvolatile memory device. The memory pins are formed on the surface of the external package and are electrically connected to the storage device.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: A soft error rate (SER) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information. A determination may be made whether the SER predicted based on the collected charge quantity at least meets a threshold. The design may be modified, and the simulation repeated, if the predicted SER value meets a threshold value. A semiconductor circuit may be manufactured based on the design if the predicted SER value is less than the threshold value.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.

Abstract: An active suspension control unit may include an actuator having an active roll stabilization (ARS) structure to variably adjust response characteristics of a suspension, and a controller for determining a driving situation of a vehicle through information input from a sensor, and determining a final desired control value of the actuator based on a desired relative suspension vertical force value set in advance according to the driving situation and a difference value generated by a difference between left and right wheel's relative suspension vertical velocities.

Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Abstract: A semiconductor integrated card includes an external package, a subscriber identification module (SIM) circuit, a plurality of SIM pins, a storage device and a plurality of memory pins. The SIM circuit is formed inside of the external package and is configured to store subscriber information. The SIM pins are formed on a surface of the external package and are electrically connected to the SIM circuit. The storage device is formed inside of the external package and is separated from the SIM circuit. The storage device includes a nonvolatile memory device. The memory pins are formed on the surface of the external package and are electrically connected to the storage device.