Abstract: A semiconductor integrated card includes an external package, a subscriber identification module (SIM) circuit, a plurality of SIM pins, a storage device and a plurality of memory pins. The SIM circuit is formed inside of the external package and is configured to store subscriber information. The SIM pins are formed on a surface of the external package and are electrically connected to the SIM circuit. The storage device is formed inside of the external package and is separated from the SIM circuit. The storage device includes a nonvolatile memory device. The memory pins are formed on the surface of the external package and are electrically connected to the storage device.

Abstract: A semiconductor integrated card includes an external package, a subscriber identification module (SIM) circuit, a plurality of SIM pins, a storage device and a plurality of memory pins. The SIM circuit is formed inside of the external package and is configured to store subscriber information. The SIM pins are formed on a surface of the external package and are electrically connected to the SIM circuit. The storage device is formed inside of the external package and is separated from the SIM circuit. The storage device includes a nonvolatile memory device. The memory pins are formed on the surface of the external package and are electrically connected to the storage device.

Abstract: A semiconductor integrated card includes an external package, a subscriber identification module (SIM) circuit, a plurality of SIM pins, a storage device and a plurality of memory pins. The SIM circuit is formed inside of the external package and is configured to store subscriber information. The SIM pins are formed on a surface of the external package and are electrically connected to the SIM circuit. The storage device is formed inside of the external package and is separated from the SIM circuit. The storage device includes a nonvolatile memory device. The memory pins are formed on the surface of the external package and are electrically connected to the storage device.

Abstract: A semiconductor integrated card includes an external package, a subscriber identification module (SIM) circuit, a plurality of SIM pins, a storage device and a plurality of memory pins. The SIM circuit is formed inside of the external package and is configured to store subscriber information. The SIM pins are formed on a surface of the external package and are electrically connected to the SIM circuit. The storage device is formed inside of the external package and is separated from the SIM circuit. The storage device includes a nonvolatile memory device. The memory pins are formed on the surface of the external package and are electrically connected to the storage device.

Abstract: A semiconductor device comprises a first non-volatile memory configured to store program code and a processor configured to copy the program code from the first non-volatile memory to a second non-volatile memory after a solder reflow process. The processor typically copies the program code from the first non-volatile memory to the second non-volatile memory after the processor is completely booted.

Abstract: A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N.

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract: A non-volatile memory device, non-volatile memory cell array and related method of operation are disclosed. The non-volatile memory cell array includes a defined data unit stored in a plurality of non-volatile memory cells capable of being electrically overwritten within the non-volatile memory cell array, and an erase marker corresponding to the data unit and indicating whether the data unit is in an erased state or a not-erased state.

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract: A nonvolatile memory device comprises overwritable memory cells. In an overwrite operation, data is read from a selected region of the nonvolatile memory device and combined with overwrite data to produce combined data. An error correction code is then generated for the combined data and the overwrite data and the error correction code are stored in the selected region.

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract: A non-volatile memory device, non-volatile memory cell array and related method of operation are disclosed. The non-volatile memory cell array includes a defined data unit stored in a plurality of non-volatile memory cells capable of being electrically overwritten within the non-volatile memory cell array, and an erase marker corresponding to the data unit and indicating whether the data unit is in an erased state or a not-erased state.

Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Abstract: A nonvolatile memory device comprises overwritable memory cells. In an overwrite operation, data is read from a selected region of the nonvolatile memory device and combined with overwrite data to produce combined data. An error correction code is then generated for the combined data and the overwrite data and the error correction code are stored in the selected region.

Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Abstract: A semiconductor device comprises a first non-volatile memory configured to store program code and a processor configured to copy the program code from the first non-volatile memory to a second non-volatile memory after a solder reflow process. The processor typically copies the program code from the first non-volatile memory to the second non-volatile memory after the processor is completely booted.

Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.