Patents by Inventor Hui Liang

Hui Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11188532
    Abstract: A computing environment is configured to divide a search query into at least a first sub-query and a second sub-query. A first service and a second service are created to execute the first sub-query and the second sub-query and identify search results from a first one and a second one of the databases, respectively, in parallel. For instance, in response to the first set of search results being placed in the first queue, the second one of the services can execute the second subquery on a second database while the first service performs subsequent queries. A final result of the search query can be generated based at least in part on the second set of search results in the second queue.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 30, 2021
    Assignee: VMWARE, INC.
    Inventors: Jong Ho Won, Karen Brems, Jiajie Liang, Gregory Bollella, Hui Xu, Arushi Gangrade
  • Publication number: 20210366833
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Publication number: 20210363254
    Abstract: The present invention relates to a pharmaceutical combination which comprises (a) at least one antibody molecule (e.g., humanized antibody molecules) that bind to Programmed Death 1 (PD-1), and (b) a HDM2-p53 interaction inhibitor, said combination for simultaneous, separate or sequential administration for use in the treatment of a proliferative disease, a pharmaceutical composition comprising such combination; a method of treating a subject having a proliferative disease comprising administration of said combination to a subject in need thereof; use of such combination for the treatment of proliferative disease; and a commercial package comprising such combination; said proliferative disease being a TP53 wildtype tumor, in particular TP53 wildtype renal cell carcinoma (RCC) or TP53 wildtype colorectal cancer (CRC).
    Type: Application
    Filed: March 18, 2019
    Publication date: November 25, 2021
    Inventors: Stephane FERRETTI, Nelson GUERREIRO, Ensar HALILOVIC, Sebastien JEAY, Astrid JULLION, Jinsheng LIANG, Christophe MEILLE, Hui-Qin WANG, Jens WUERTHNER
  • Publication number: 20210359174
    Abstract: In an embodiment a method includes providing a light-emitting diode chip and a phosphor body, applying a sacrificial layer to a top side of the phosphor body only, placing the phosphor body onto the light-emitting diode chip, molding an encapsulation body directly around the light-emitting diode chip and the phosphor body by a film assisted molding, wherein at least in places a top face of the sacrificial layer facing away from the phosphor body remains unsealed with a molding film, and removing the sacrificial layer so that the top side of the phosphor body is free of the sacrificial layer.
    Type: Application
    Filed: October 22, 2018
    Publication date: November 18, 2021
    Inventors: Mei See Boon, Hui Chiang Teoh, Tomin Liu, Hui Ying Pee, Asliza Alias, Lay Teng Tan, Yuan Liang, Alex Kheng Hooi Lim, Wing Yew Wong
  • Publication number: 20210358284
    Abstract: A visible-light-image physiological monitoring system with thermal detecting assistance is disclosed. The system takes a visible-light image and a thermal image of a body at the same time. A processing unit identifies a body feature of the visible-light image and determines a coordinate of the feature. In a learning mode, an initial temperature of the body feature is determined from the thermal image according to the coordinate of the body feature. After then, a physiological status monitoring mode is executed to monitor the temperature changes of the body feature and output an alarm when the temperature is determined to be abnormal. Therefore, a monitoring accuracy of the visible-light-image physiological monitoring system is increased and avoids transmitting false alarms or no alarms.
    Type: Application
    Filed: December 30, 2020
    Publication date: November 18, 2021
    Inventors: Chih-Hsin TSENG, Shih-Yun SHEN, Hsin-Yi LIN, Kang-Ning SHAN, Hsueh-Fa HSU, Por-Sau LIN, Chien-Yu CHEN, Tzu Ling LIANG, Huan-Yun WU, Yu-Chiao WANG, Chien-Hui HSU
  • Patent number: 11171285
    Abstract: Provided is a non-ferromagnetic spacing composite layer, comprising first, second and third spacing layers stacked in sequence. The first and third spacing layers are each made of Re, Rh, Ir, W, Mo, Ta, or Nb, and the second spacing layer is made of Ru. The second spacing layer has a thickness of equal to or more than 0.18 nm, and the non-ferromagnetic spacing composite layer has a total thickness of 0.6 nm to 1 nm. Also, provided are a method of preparing the non-ferromagnetic spacing composite layer, a synthetic antiferromagnetic laminated structure, and an MRAM. The synthetic antiferromagnetic laminated structure can maintain a certain coupling strength and the RKKY indirect interaction after thermal treatment, thereby keeping the recording function of MRAM.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 9, 2021
    Assignee: SOLAR APPLIED MATERIALS TECHNOLOGY CORP.
    Inventors: Chih-Huang Lai, Chun-Liang Yang, Yi-Huan Chung, Wei-Chih Huang, Chih-Wen Tang, Hui-Wen Cheng
  • Patent number: 11171100
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a seed layer to cover a first passivation layer over a semiconductor substrate. The method also includes forming a metal layer to partially cover the seed layer by using the seed layer as an electrode layer in a first plating process and forming a metal pillar bump over the metal layer by using the seed layer as an electrode layer in a second plating process. In addition, the method includes forming a second passivation layer over the metal layer, wherein the second passivation layer includes a protrusion portion extending from a top surface of the second passivation layer and surrounding the sidewall of the metal pillar bump.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Hui-Min Huang, Wei-Hung Lin, Wen-Hsiung Lu, Ming-Da Cheng, Chang-Jung Hsueh, Kuan-Liang Lai
  • Publication number: 20210343715
    Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Inventors: Guo-Huei WU, Jerry Chang-Jui KAO, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jung-Chan YANG, Lee-Chung LU, Xiangdong CHEN
  • Publication number: 20210338414
    Abstract: A tissue repair device and a method for using the same are provided. The tissue repair device includes a body portion and at least one wire. The body portion includes an inner layer and an outer layer. The inner layer is close to a tissue, wherein the inner layer includes a hydrophilic structure, and the outer layer includes a hydrophobic structure. The wire is connected to the body portion to fix the body portion to the tissue.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 4, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Chieh HUANG, Jeng-Liang KUO, Hui-Ting HUANG, Shiun-Yin CHANG, Meng-Hsueh LIN, Cheng-Yi WU, Lih-Tao HSU, Pei-I TSAI, Hsin-Hsin SHEN, Chih-Yu CHEN, Kuo-Yi YANG, Chun-Hsien MA
  • Patent number: 11162643
    Abstract: A single-point dual sensor-based leakage method and system for a gas-liquid stratified flow pipeline includes a single-point dual sensor-based leakage formula for a pipeline to be detected; installing two sensors at the same point of one end of the pipeline, a signal collected by the bottom sensor being an acoustic wave propagated by liquid in the pipeline, and a signal collected by the top sensor being an acoustic wave propagated by gas in the pipeline; processing the two acoustic waves to obtain a time difference; and substituting the acoustic velocity in a gas and the time difference into the single-point dual sensor-based leakage formula. The installation of sensors at two ends of a pipeline, avoids missing detection of leakage acoustic wave signals by a single sensor, reduces the number of installed sensors, and is low in cost, high in safety and strong in applicability to a gas-liquid stratified flow pipeline.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: November 2, 2021
    Assignee: CHINA UNIVERSITY OF PETROLEUM (EAST CHINA)
    Inventors: Yuxing Li, Cuiwei Liu, Lingya Meng, Qihui Hu, Hui Han, Liping Fang, Wuchang Wang, Huafei Jing, Yazhen Wang, Jie Liang
  • Publication number: 20210335616
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Application
    Filed: July 8, 2021
    Publication date: October 28, 2021
    Inventors: Hong-Ying LIN, Cheng-Yi WU, Alan TU, Chung-Liang CHENG, Li-Hsuan CHU, Ethan HSIAO, Hui-Lin SUNG, Sz-Yuan HUNG, Sheng-Yung LO, C.W. CHIU, Chih-Wei HSIEH, Chin-Szu LEE
  • Patent number: 11155376
    Abstract: A cigarette filter rod boxing machine, including a cigarette filter rod holding mechanism and a cigarette filter rod pushing mechanism. The cigarette filter rod holding mechanism includes a lifting groove and a lifting power mechanism. The cigarette filter rod pushing mechanism includes a bottom plate, a middle push plate, a middle push vertical plate, an upper push plate, and an upper push plate limiting mechanism. The middle push vertical plate is vertically fixed on one side of the middle push plate, and the other side of the middle push vertical plate is precisely opposite to the other side of the U-shaped groove body. The first power mechanism used for controlling the middle push plate and the components on the middle push plate to advance to or return from the inside of the lifting groove is arranged between the bottom plate and the middle push plate.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 26, 2021
    Assignee: ZHENGZHOU HAIYI TECHNOLOGY CO. LTD.
    Inventors: Haiping Zhang, Jianfang Wang, Hui Liang, Xudong Zeng, Shuhua Zhao, Juqing Liu, Yizhen Chang, Kexin Shui
  • Patent number: 11143742
    Abstract: A digital receiving apparatus includes an analog-to-digital conversion module, a polyphase filter module, a fast Fourier transform module and a phase compensation module, which transforms signals of a target radio source from time domain to frequency domain. It further includes a standard time acquisition module configured to acquire a standard timestamp, a communication module configured to communicate with a host computer, a delay parameter temporary storage module configured to store a to-be-compensated delay parameter, a control enable module configured to generate an enable signal, a delay module configured to perform delay, and a phase parameter generation module configured to temporarily store the to-be-compensated delay parameter and convert it into a phase compensation parameter.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: October 12, 2021
    Assignees: INSTITUTE OF AUTOMATION, CHINESE ACADEMY OF SCIENCES;, GUANGZHOU ARTIFICIAL INTELLIGENCE AND ADVANCED COMPUTING INSTITUTE OF CASIA
    Inventors: Lin Shu, Jie Hao, Jun Liang, Yafang Song, Liangtian Zhao, Qiuxiang Fan, Hui Feng, Wenqing Hu
  • Patent number: 11145730
    Abstract: A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Chih-Yang Yeh, Jeng-Ya David Yeh
  • Publication number: 20210313437
    Abstract: A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Chih-Yang YEH, Shu-Hui WANG, Jeng-Ya David YEH
  • Publication number: 20210312007
    Abstract: Various examples are disclosed for hybrid alert and action solution in IoT (IoT) networks. A cloud layer decision model that generates cloud layer predictions is identified using device layer data. A quantized decision model is generated as a quantized version of the cloud layer decision model. A logical group that includes an edge device that collects a portion of the device layer data is identified. The quantized decision model is transmitted to the logical group.
    Type: Application
    Filed: May 3, 2021
    Publication date: October 7, 2021
    Inventors: Hui Xu, Jiajie Liang, Jong Ho Won
  • Publication number: 20210313972
    Abstract: An input circuit of a flip-flop includes: a first gate strip, a second gate strip and a third gate strip. The first gate strip is a co-gate terminal of a first PMOS and a first NMOS; the second gate strip is disposed immediately adjacent to the first gate strip, and a co-gate terminal of a second PMOS and a second NMOS. The first PMOS and the second PMOS share a doping region as a co-source terminal. The first NMOS and the second NMOS share a doping region as a co-source terminal. The third gate strip is disposed immediately adjacent to the second gate strip. The third gate strip is a co-gate terminal of a third PMOS and a third NMOS. The second PMOS and the third PMOS share a doping region as a co-drain terminal. The second NMOS and the third NMOS share a doping region as a co-drain terminal.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventors: JIN-WEI XU, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN
  • Patent number: 11131976
    Abstract: A system, method and gateway are provided. The method is executed by a primary gateway, and includes obtaining status information from smart devices, a first portion of which belong to and communicate with the primary gateway using a first standard, and a second portion of which belong to and communicate with a secondary gateway using a second standard. The status information from the smart devices belonging to the secondary gateway is received from the secondary gateway, and the status information from the smart devices belonging to the primary gateway is received directly from the smart devices belonging to the primary gateway. A control instruction for controlling a second smart device is generated in response to status information from a first smart device complying with an interworking rule, where the first and second smart devices communicate using different standards. The control instruction is transmitted to the second smart device.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: September 28, 2021
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Xin Yang, Xiao Qing Liang, Kai Qian, Hua Mao, Chao Hui Ding
  • Patent number: 11133255
    Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Publication number: 20210294296
    Abstract: Various examples are disclosed for hybrid alert and action solution in Internet-of-Things (IoT) networks. A multi-edge alert definition specifies a plurality of IoT devices that communicate through a plurality of edge devices. The multi-edge alert definition is registered in a fog evaluation service for evaluation. Data corresponding to the IoT devices is received by the fog evaluation service from the plurality of edge devices. An alert is triggered based on a condition specified in the multi-edge alert definition.
    Type: Application
    Filed: March 23, 2020
    Publication date: September 23, 2021
    Inventors: Hui Xu, Jiajie Liang, Karen Brems, Jong Ho Won