Abstract: A method for improving the adhesion of a thick silicon nitride layer, to an underlying spin on glass, (SOG), layer, has been developed. After applying, baking and curing of a SOG layer, plasma treatment of the SOG layer, is performed in a deposition tool, using a nitrous oxide plasma. The plasma treatment prepares the exposed SOG surface for an in situ deposition of a thick silicon nitride layer, by improving the adhesion of thick silicon nitride to the underlying SOG layer, and by decreasing the possibility of silicon nitride delamination, that can occur with counterparts, fabricated without the nitrous oxide plasma treatment of the SOG layer.

Abstract: A multi-step chemical-mechanical polishing method for improving tungsten chemical-mechanical polishing (CMP) process is provided in the present invention. The method comprises following steps. First, a wafer is placed on a first pad of a CMP system, wherein a head fixes the wafer on the first pad. Then, the head is rotated and the wafer is polished on the first pad by using a tungsten slurry. Next, the wafer is transferred to place on a second pad of the CMP system, wherein the head fixes the wafer on the second pad. Following, the head is rotated and the wafer is polished on the second pad by using the tungsten slurry. Then, the wafer is cleaned on the second pad by using a de-ionic water. Next, the wafer is transferred to place on a third pad of the CMP system, wherein the head fixes the wafer on the third pad. Following, the wafer is cleaned on the third pad by using the de-ionic water.

Abstract: A method for forming a microelectronic layer. There is first provided a substrate. There is then formed over the substrate the microelectronic layer while employing a plasma enhanced chemical vapor deposition (PECVD) method employing a source material gas and a carrier gas, wherein there is employed a sufficiently low plasma power, a sufficiently low source material gas:carrier gas flow rate ratio and a sufficiently high carrier gas atomic mass such that the microelectronic layer is formed with enhanced film thickness uniformity. The method may be employed for forming ion implant screen layers, such as silicon oxide ion implant screen layers, with enhanced film thickness uniformity.

Abstract: A method to prevent the accumulation of particle impurities on the surface of a semiconductor substrate that contains wolfram plugs during the process of polishing the surface of the wafer. The polishing sequence consists of three distinct polishing steps whereby the first two steps use hard polishing pads while the third step uses a soft polishing pad with the application of slurry during the third polish.

Abstract: A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench.

Abstract: A method is described for improving the step coverage of tungsten interconnects and plugs when deposited at low temperatures into contact/via openings having high aspect ratios. The depositions are made at pressures between 4.5 and 100 Torr in a CVD tool. The method includes a first nucleation step, and a second step for filling the contact/via openings wherein deposition conditions favor good step coverage. For forming an interconnect and a third deposition step, providing moderate step coverage and low stress, is used to build up the interconnect. The high pressures permit deposition at practical rates at low temperatures. In addition the high pressures also permit application of backside gas pressure to the wafer during deposition, thereby improving the thermal contact between the wafer and the heated substrate holder. This contributes significantly to stress reduction and improved step coverage.