Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: A folding lens system includes: a polarization-dependence device, a first optical device, a first polarization controller, a second optical device and a second polarization controller. The polarization-dependence device has a first surface and a second surface opposite to the first surface. The first optical device is located at a side facing toward the first surface of the polarization-dependence device. The first polarization controller is located between the polarization-dependence device and the first optical device. The first polarization controller has the same curvature as the first surface of the polarization-dependence device. The second optical device is located at a side facing toward the second surface of the polarization-dependence device. The second polarization controller is located between the polarization-dependence device and the second optical device. The second polarization controller has the same curvature as the second surface of the polarization-dependence device.

Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: A microelectromechanical system (MEMS) device includes a substrate and at least one MEMS unit disposed on the substrate. The MEMS unit includes at least one first electrode, at least one second electrode, at least one landing element, and a hinge layer. The first electrode is disposed on the substrate. The second electrode is disposed on the substrate. The landing element is disposed on the substrate. The hinge layer includes a hinge portion and at least one cantilever portion. The hinge portion is connected to the second electrode. The cantilever portion is connected to the hinge portion. The cantilever portion has a first opening and at least one spring disposed in the first opening and connected to at least one side of the first opening. When a voltage difference exists between the first electrode and the second electrode, the hinge portion is distorted and the spring thus touches the landing element.

Abstract: A microelectromechanical system (MEMS) device includes a substrate and at least one MEMS unit disposed on the substrate. The MEMS unit includes at least one first electrode, at least one second electrode, at least one landing element, and a hinge layer. The first electrode is disposed on the substrate. The second electrode is disposed on the substrate. The landing element is disposed on the substrate. The hinge layer includes a hinge portion and at least one cantilever portion. The hinge portion is connected to the second electrode. The cantilever portion is connected to the hinge portion. The cantilever portion has a first opening and at least one spring disposed in the first opening and connected to at least one side of the first opening. When a voltage difference exists between the first electrode and the second electrode, the hinge portion is distorted and the spring thus touches the landing element.

Abstract: A mixed-mode process introduces a hard mask layer. Due to the introduced hard mask layer made of non-resist material formed over devices, performance of a formed capacitor is protected from effects of an implantation process such as source/drain implantation. A self-aligned silicide (salicide) process for a MOSFET transistor can also be performed. Thus, production efficiency and performance of an IC product formed by the mixed-mode process can be improved. Moreover, the number of required fabrication steps is reduced and cost savings can be realized.

Abstract: A mixed-mode process introduces a hard mask layer. Due to the introduced hard mask layer made of non-resist material formed over devices, performance of a formed capacitor is protected from effects of an implantation process such as source/drain implantation. A self-aligned silicide (salicide) process for a MOSFET transistor can also be performed. Thus, production efficiency and performance of an IC product formed by the mixed-mode process can be improved. Moreover, the number of required fabrication steps is reduced and cost savings can be realized.

Abstract: Within a reflective liquid crystal on silicon display image array optoelectronic microelectronic fabrication there is employed a polyimide alignment layer formed upon a reflection enhancing layer. The reflective liquid crystal on silicon display image array optoelectronic microelectronic fabrication is fabricated with enhanced liquid crystal material alignment and enhanced contrast.

Abstract: A method of forming a CVD nitride (e.g., titanium nitride) film on a substrate. The as-deposited nitride film is treated by a plasma of a high power density (preferably between approximately 200 W and 300 W) for a prolonged duration of time (preferably between approximately 32 s and 52 s) to reduce the tendency of the resistance and thickness of the as-deposited film to change because of either time of exposure to atmosphere or subsequent processing steps.

Abstract: A method of reducing tungsten plug loss in processes for fabrication for silicon-based semiconductor devices that include a tungsten plug in a high aspect ratio contact hole. The invention provides a barrier layer prepared by first forming a conformal layer of titanium nitride by chemical vapor deposition. Afterward, another film of titanium nitride is supplied by plasma vapor deposition. The barrier layer comprises at least these two films, and tungsten is then deposited to at least fill the high aspect ratio film-coated contact hole. Upon removal of excess tungsten as by wet etch back, the tungsten plug remains essentially intact, and any plug loss is insignificant in comparison with the prior art.