Abstract: A semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, a seal ring structure including first and second interconnect structures, and a passivation layer on the seal ring structure and the second dielectric layer. The first interconnect structure is located in the first dielectric layer. The second interconnect structure is located in the second dielectric layer and connected to the first interconnect structure. The passivation layer has a spacer portion covering a sidewall of the second dielectric layer and a portion of the first dielectric layer. A ditch exists in the passivation layer and the first dielectric layer. The spacer portion is located between the ditch and the seal ring structure. The semiconductor structure is able to reduce time and power of an etching process for forming the ditch.

Abstract: A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.

Abstract: A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.

Abstract: An apparatus comprises a first port, a second port, a battery, and a power control unit electrically connected to the battery, the first port and the second port. The power control unit is configured to, on the basis of an output from the battery: transmit a first power signal to the first port and transmit a second power signal to the second port; or transmit a third power signal received by the first port to the second port.

Abstract: A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.

Abstract: A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.

Abstract: A capacitive keyboard device with a keystroke triggering threshold adaptively adjustable capability is proposed, which is designed for integration to an electronic unit, such as PDA (Personal Digital Assistant) computers, mobile phone unit, and calculator, for use as a data input device for the electronic unit. The proposed capacitive keyboard device is characterized by the operation of a triggering threshold adaptive adjustment function that can adaptively adjust the keystroke triggering threshold of the capacitive keyboard device in response to the user's habitual key-pressing action during each use, which also takes account of all internal factors (such as decay of the capacitor structure) and external factors (such as physical characteristics of the user's fingers). This feature allows the capacitive keyboard device to be reliable in operation for long period of use.

Abstract: A capacitive keyboard device with a keystroke triggering threshold adaptively adjustable capability is proposed, which is designed for integration to an electronic unit, such as PDA (Personal Digital Assistant) computers, mobile phone unit, and calculator, for use as a data input device for the electronic unit. The proposed capacitive keyboard device is characterized by the operation of a triggering threshold adaptive adjustment function that can adaptively adjust the keystroke triggering threshold of the capacitive keyboard device in response to the user's habitual key-pressing action during each use, which also takes account of all internal factors (such as decay of the capacitor structure) and external factors (such as physical characteristics of the user's fingers). This feature allows the capacitive keyboard device to be reliable in operation for long period of use.

Abstract: A method for wafer level stack die placement is disclosed. At first, a wafer including a plurality of dice is provided. The wafer is adhered to a photosensitive adhesive tape. The wafer is attached on a die carrier to fix at least one die from the wafer on the die carrier. The die carrier may be another wafer. The photosensitive adhesive tape is selectively exposed to form an adhesion-released portion. The adhesion-released portion is aligned with the fixed die. Then, the photosensitive adhesive tape and the die carrier with the fixed die are apart. Therefore the stack die placement in the die-attaching batch is quick and efficient.

Abstract: A method for wafer level stack die placement is disclosed. At first, a wafer including a plurality of dice is provided. The wafer is adhered to a photosensitive adhesive tape. The wafer is attached on a die carrier to fix at least one die from the wafer on the die carrier. The die carrier may be another wafer. The photosensitive adhesive tape is selectively exposed to form an adhesion-released portion. The adhesion-released portion is aligned with the fixed die. Then, the photosensitive adhesive tape and the die carrier with the fixed die are apart. Therefore the stack die placement in the die-attaching batch is quick and efficient.

Abstract: A method for controlling the adhesive distribution in a flip-chip semiconductor product has steps: (a) providing a substrate with a flip-chip electrically mounted on the substrate via multiple bumps, (b) providing an dam along an edge of the flip-chip, and (c) depositing adhesive on the dam to flow into a space between the substrate and a bottom of the flip-chip by capillary effect. The shape of the dam is determined by the density of the multiple bumps to control the flowing speed of the adhesive to obtain a good adhesive distribution.