Patents by Inventor Hui Min LER

Hui Min LER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230073330
    Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.
    Type: Application
    Filed: November 17, 2022
    Publication date: March 9, 2023
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hui Min LER, Soon Wei WANG, Chee Hiong CHEW
  • Publication number: 20230073773
    Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.
    Type: Application
    Filed: November 16, 2022
    Publication date: March 9, 2023
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hui Min LER, Soon Wei WANG, Chee Hiong CHEW
  • Patent number: 11557530
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: January 17, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Swee Har Khor, Tian Hing Lim, Hui Min Ler, Chee Hiong Chew, Phillip Celaya
  • Patent number: 11532539
    Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: December 20, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hui Min Ler, Soon Wei Wang, Chee Hiong Chew
  • Publication number: 20220208658
    Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hui Min LER, Soon Wei WANG, Chee Hiong CHEW
  • Publication number: 20200312749
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 1, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Swee Har KHOR, Tian Hing LIM, Hui Min LER, Chee Hiong CHEW, Phillip CELAYA
  • Patent number: 10727170
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: July 28, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Swee Har Khor, Tian Hing Lim, Hui Min Ler, Chee Hiong Chew, Phillip Celaya
  • Publication number: 20180090421
    Abstract: A method for plating package leads, in some embodiments, comprises: providing a package having a lead electrically coupled to a tie bar; singulating said lead; electroplating said singulated lead using the tie bar; and singulating said tie bar.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Nam Khong THEN, Hui Min LER, Phillip CELAYA, Chee Hiong CHEW
  • Publication number: 20170062310
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Application
    Filed: September 1, 2015
    Publication date: March 2, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Swee Har KHOR, Tian Hing LIM, Hui Min LER, Chee Hiong CHEW, Phillip CELAYA