Patents by Inventor Hui-Min Wu
Hui-Min Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10927000Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.Type: GrantFiled: October 17, 2016Date of Patent: February 23, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Che Chen, Te-Yuan Wu, Chia-Huei Lin, Hui-Min Wu, Kun-Che Hsieh, Kuan-Yu Wang, Chung-Yi Chiu
-
Patent number: 9988264Abstract: A method of fabricating an integrated structure for MEMS device and semiconductor device comprises steps of: providing a substrate having a transistor thereon in a semiconductor device region and a first MEMS component thereon in a MEMS region; performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers; forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in a etch stopping device region; forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and performing an etching process to remove the third dielectric layers in the MEMS region.Type: GrantFiled: September 18, 2014Date of Patent: June 5, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Bang-Chiang Lan, Li-Hsun Ho, Wei-Cheng Wu, Hui-Min Wu, Min Chen, Tzung-I Su, Chien-Hsin Huang
-
Patent number: 9783408Abstract: A structure of micro-electro-mechanical systems (MEMS) electroacoustic transducer is disclosed. The MEMS electroacoustic transducer includes a substrate having a MEMS device region, a diaphragm having openings and disposed in the MEMS device region, a silicon material layer disposed on the diaphragm and sealing the diaphragm, and a conductive pattern disposed beneath the diaphragm in the MEMS device region. Preferably, a first cavity is also formed between the diaphragm and the substrate.Type: GrantFiled: June 18, 2014Date of Patent: October 10, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Bang-Chiang Lan, Ming-I Wang, Li-Hsun Ho, Hui-Min Wu, Min Chen, Chien-Hsin Huang
-
Publication number: 20170036905Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.Type: ApplicationFiled: October 17, 2016Publication date: February 9, 2017Inventors: Li-Che Chen, Te-Yuan Wu, Chia-Huei Lin, Hui-Min Wu, Kun-Che Hsieh, Kuan-Yu Wang, Chung-Yi Chiu
-
Patent number: 9499399Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.Type: GrantFiled: June 14, 2013Date of Patent: November 22, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Che Chen, Te-Yuan Wu, Chia-Huei Lin, Hui-Min Wu, Kun-Che Hsieh, Kuan-Yu Wang, Chung-Yi Chiu
-
Patent number: 8936960Abstract: A method for fabricating an integrated device includes the following steps. First, a multi-layered structure is formed on a substrate, wherein the multi-layered structure is embedded in a lower isolation layer. Then, a bottom conductive pattern and a top conductive pattern are formed on a top surface of the lower isolation layer, wherein the top conductive pattern is on a top surface of the bottom conductive pattern. Afterwards, portions of the top conductive pattern are removed to expose portions of the bottom conductive pattern. Subsequently, an upper isolation layer is deposited on the lower isolation layer so that the upper isolation layer can be in direct contact with the portions of the bottom conductive pattern. Finally, portions of the lower isolation layer and the upper isolation layer are removed so as to expose portions of the substrate.Type: GrantFiled: July 2, 2013Date of Patent: January 20, 2015Assignee: United Microelectronics Corp.Inventors: Kuan-Yu Wang, Hui-Min Wu, Kun-Che Hsieh
-
Publication number: 20150011035Abstract: A method for fabricating an integrated device includes the following steps. First, a multi-layered structure is formed on a substrate, wherein the multi-layered structure is embedded in a lower isolation layer. Then, a bottom conductive pattern and a top conductive pattern are formed on a top surface of the lower isolation layer, wherein the top conductive pattern is on a top surface of the bottom conductive pattern. Afterwards, portions of the top conductive pattern are removed to expose portions of the bottom conductive pattern. Subsequently, an upper isolation layer is deposited on the lower isolation layer so that the upper isolation layer can be in direct contact with the portions of the bottom conductive pattern. Finally, portions of the lower isolation layer and the upper isolation layer are removed so as to expose portions of the substrate.Type: ApplicationFiled: July 2, 2013Publication date: January 8, 2015Inventors: Kuan-Yu Wang, Hui-Min Wu, Kun-Che Hsieh
-
Publication number: 20150004732Abstract: A method of fabricating an integrated structure for MEMS device and semiconductor device comprises steps of: providing a substrate having a transistor thereon in a semiconductor device region and a first MEMS component thereon in a MEMS region; performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers; forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in a etch stopping device region; forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and performing an etching process to remove the third dielectric layers in the MEMS region.Type: ApplicationFiled: September 18, 2014Publication date: January 1, 2015Inventors: Bang-Chiang Lan, Li-Hsun Ho, Wei-Cheng Wu, Hui-Min Wu, Min Chen, Tzung-I Su, Chien-Hsin Huang
-
Publication number: 20140367805Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.Type: ApplicationFiled: June 14, 2013Publication date: December 18, 2014Inventors: Li-Che Chen, Te-Yuan Wu, Chia-Huei Lin, Hui-Min Wu, Kun-Che Hsieh, Kuan-Yu Wang, Chung-Yi Chiu
-
Patent number: 8872287Abstract: The present invention relates to an integrated structure for a MEMS device and a semiconductor device and a method of fabricating the same, in which an etch stopping element is included on a substrate between the MEMS device and the semiconductor device for protecting the semiconductor device from lateral damage when an oxide releasing process is performed to fabricate the MEMS device. The etch stopping element has various profiles and is selectively formed by an individual fabricating process or is simultaneously formed with the semiconductor device in the same fabricating process. It is a singular structure or a combined stacked multilayered structure, for example, a plurality of rows of pillared etch-resistant material plugs, one or a plurality of wall-shaped etch-resistant material plugs, or a multilayered structure of a stack of which and an etch-resistant material layer.Type: GrantFiled: March 27, 2008Date of Patent: October 28, 2014Assignee: United Microelectronics Corp.Inventors: Bang-Chiang Lan, Li-Hsun Ho, Wei-Cheng Wu, Hui-Min Wu, Min Chen, Tzung-I Su, Chien-Hsin Huang
-
Patent number: 8865500Abstract: A method of fabricating a MEMS microphone includes: first providing a substrate having a first surface and a second surface. The substrate is divided into a logic region and a MEMS region. The first surface of the substrate is etched to form a plurality of first trenches in the MEMS region. An STI material is then formed in the plurality of first trenches. Subsequently, the second surface of the substrate is etched to form a second trench in the MEMS region, wherein the second trench connects with each of the first trenches. Finally, the STI material in the first trenches is removed.Type: GrantFiled: February 3, 2010Date of Patent: October 21, 2014Assignee: United Microelectronics Corp.Inventors: Chien-Hsin Huang, Bang-Chiang Lan, Hui-Min Wu, Tzung-I Su, Chao-An Su, Tzung-Han Tan
-
Publication number: 20140291787Abstract: A structure of micro-electro-mechanical systems (MEMS) electroacoustic transducer is disclosed. The MEMS electroacoustic transducer includes a substrate having a MEMS device region, a diaphragm having openings and disposed in the MEMS device region, a silicon material layer disposed on the diaphragm and sealing the diaphragm, and a conductive pattern disposed beneath the diaphragm in the MEMS device region. Preferably, a first cavity is also formed between the diaphragm and the substrate.Type: ApplicationFiled: June 18, 2014Publication date: October 2, 2014Inventors: Bang-Chiang Lan, Ming-I Wang, Li-Hsun Ho, Hui-Min Wu, Min Chen, Chien-Hsin Huang
-
Patent number: 8798291Abstract: A structure of a micro-electro-mechanical systems (MEMS) electroacoustic transducer includes a substrate, a diaphragm, a silicon material layer, and a conductive pattern. The substrate includes an MEMS device region. The diaphragm has openings, and is disposed in the MEMS device region. A first cavity is formed between the diaphragm and the substrate. The silicon material layer is disposed on the diaphragm and seals the diaphragm. The conductive pattern is disposed beneath the diaphragm in the MEMS device region.Type: GrantFiled: September 19, 2008Date of Patent: August 5, 2014Assignee: United Microelectronics Corp.Inventors: Bang-Chiang Lan, Ming-I Wang, Li-Hsun Ho, Hui-Min Wu, Min Chen, Chien-Hsin Huang
-
Patent number: 8710601Abstract: A micro electro mechanical system (MEMS) structure is disclosed. The MEMS structure includes a backplate electrode and a 3D diaphragm electrode. The 3D diaphragm electrode has a composite structure so that a dielectric is disposed between two metal layers. The 3D diaphragm electrode is adjacent to the backplate electrode to form a variable capacitor together.Type: GrantFiled: November 19, 2009Date of Patent: April 29, 2014Assignee: United Microelectronics Corp.Inventors: Chien-Hsin Huang, Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Min Chen, Meng-Jia Lin
-
Patent number: 8642986Abstract: An integrated circuit (IC) having a microelectromechanical system (MEMS) device buried therein is provided. The integrated circuit includes a substrate, a metal-oxide semiconductor (MOS) device, a metal interconnect, and the MEMS device. The substrate has a logic circuit region and a MEMS region. The MOS device is located on the logic circuit region of the substrate. The metal interconnect, formed by a plurality of levels of wires and a plurality of vias, is located above the substrate to connect the MOS device. The MEMS device is located on the MEMS region, and includes a sandwich membrane located between any two neighboring levels of wires in the metal interconnect and connected to the metal interconnect.Type: GrantFiled: September 23, 2009Date of Patent: February 4, 2014Assignee: United Microelectronics Corp.Inventors: Tzung-Han Tan, Bang-Chiang Lan, Ming-I Wang, Tzung-I Su, Chien-Hsin Huang, Hui-Min Wu, Chao-An Su, Min Chen, Meng-Jia Lin
-
Patent number: 8587078Abstract: A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.Type: GrantFiled: April 6, 2010Date of Patent: November 19, 2013Assignee: United Microelectronics Corp.Inventors: Chien-Hsin Huang, Li-Che Chen, Ming-I Wang, Bang-Chiang Lan, Tzung-Han Tan, Hui-Min Wu, Tzung-I Su
-
Patent number: 8558336Abstract: A semiconductor photodetector structure is provided. The structure includes a substrate, a photodetecting element and a semiconductor layer disposed on the photodetecting element. The substrate includes a first semiconductor material and includes a deep trench. The surface of the deep trench includes a first type dopant. The photodetecting element is disposed in the deep trench. The photodetecting element includes a second semiconductor material. The semiconductor layer includes a second type dopant.Type: GrantFiled: August 17, 2009Date of Patent: October 15, 2013Assignee: United Microelectronics Corp.Inventors: Tzung-I Su, Bang-Chiang Lan, Chao-An Su, Hui-Min Wu, Ming-I Wang, Chien-Hsin Huang, Tzung-Han Tan, Min Chen, Meng-Jia Lin, Wen-Yu Su
-
Patent number: 8525354Abstract: A bond pad structure comprises an interconnection structure and an isolation layer. The dielectric layer has an opening and a metal pad. The isolation layer is disposed on the interconnection structure and extends into the opening until it is in contact with the metal pad, whereby the sidewalls of the opening is blanketed by the isolation layer, and a portion of the metal pad is exposed from the opening.Type: GrantFiled: October 13, 2011Date of Patent: September 3, 2013Assignee: United Microelectronics CorporationInventors: Hui-Min Wu, Ming-I Wang, Kuan-Yu Wang, Kun-Che Hsieh, Chien-Hsin Huang
-
Patent number: 8502382Abstract: A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.Type: GrantFiled: April 30, 2012Date of Patent: August 6, 2013Assignee: United Microelectronics Corp.Inventors: Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Min Chen, Chien-Hsin Huang, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Li-Che Chen, Meng-Jia Lin
-
Publication number: 20130093104Abstract: A bond pad structure comprises an interconnection structure and an isolation layer. The dielectric layer has an opening and a metal pad. The isolation layer is disposed on the interconnection structure and extends into the opening until it is in contact with the metal pad, whereby the sidewalls of the opening is blanketed by the isolation layer, and a portion of the metal pad is exposed from the opening.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Hui-Min WU, Ming-I Wang, Kuan-Yu Wang, Kun-Che Hsieh, Chien-Hsin Huang