Abstract: The present invention discloses a control method for a hybrid density memory storage device. The method arranges physical locations for a file system stored in the storage device. The storage device includes a high density storage space, a low density storage space and a hot list capable of recording a plurality of logical locations. The method includes the following steps: receiving a command; verifying whether the logical location of the command belongs to the logical locations recorded in the hot list; and according to the verification, assigning a physical location of the high density storage space or a physical location of the low density storage space as the physical location corresponding to the logical location of the command.

Abstract: A storage device capable of meeting the reliability has a storage capacity and the reliability of the storage device is defined. The storage device includes at least one first storage unit, at least one second storage unit, and a control unit. The first storage unit forms the storage capacity of the storage device. The second storage unit is allocated to form a spare capacity according to the storage capacity and the reliability. The second storage unit replaces the bad blocks in the first storage unit. The control unit controls the first storage unit and the second storage unit to transmit and convert the data with an application system. Thereby, by allocating the spare capacity of the second storage unit, the different reliability requirement is met, and the storage capacity of the first storage unit is unaffected.

Abstract: A barrier control scheme controls the order dependency of items in a multiple FIFO queue structure. The barrier control scheme includes a cycle ID generator, a barrier bit/barrier ID generator and a cycle ID and barrier ID comparator. Each incoming item to the FIFOs is assigned a cycle ID. If an incoming item of a first FIFO has order dependency on items of a second FIFO, a barrier bit is set and a barrier ID is determined and generated by the barrier bit/barrier ID generator. The barrier bit and barrier ID are inserted in the first FIFO along with other fields of the incoming item. When an item is to be consumed, the cycle ID and barrier ID comparator compares its barrier ID and the cycle IDs of items in the second FIFO. The item to be consumed is blocked until all items on which the item is dependent are consumed in the second FIFO.

Abstract: All memory commands are classified into two categories: background commands and foreground commands, depending on whether they are data related or not. The pointed background command and foreground commands are issued onto the DRAM bus at the earliest time when the required constrains are met. The background and foreground FSM controllers work in a pipelined or overlapped manner.